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VDD

ISNS

GDRV

GND

COMP

TPS40200

SENSE

OUT

R1 R2

100

0 0.5 1 1.5 2 2.5 3

LoadCurrent- A

Efficiency-%

V =8V

V =12V

V =16V

V =5V

OUT

TPS40200-Q1

www.ti.com

SLUS739E –SEPTEMBER 2006–REVISED JULY 2013

WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER

Check for Samples: TPS40200-Q1

FEATURES

DESCRIPTION

The TPS40200 is a flexible nonsynchronous

• Qualified for Automotive Applications

controller with a built-in 200-mA driver for P-channel

• Input Voltage Range 4.5 V to 52 V

FETs. The circuit operates with inputs up to 52 V,

• Output Voltage (700 mV to 90% V

)

with a power-saving feature that turns off driver

current once the external FET has been fully turned

• 200-mA Internal P-FET Driver

on. This feature extends the flexibility of the device,

• Voltage Feed-Forward Compensation

allowing it to operate with an input voltage up to 52 V

• Undervoltage Lockout (UVLO)

without dissipating excessive power. The circuit

operates with voltage-mode feedback and has feed-

• Programmable Fixed-Frequency (35-

forward input-voltage compensation that responds

kHz to 500-kHz) Operation

instantly to input voltage change. The integral 700-

• Programmable Short-Circuit Protection

mV reference is trimmed to 2%, providing the means

• Hiccup Overcurrent Fault Recovery

to accurately control low voltages. The TPS40200 is

available in an 8-pin SOIC and supports many of the

• Programmable Closed Loop Soft Start

features of more complex controllers. Clock

• 700-mV 1% Reference Voltage

frequency, soft start, and overcurrent limit are each

• External Synchronization

easily programmed by a single, external component.

The part has undervoltage lockout (UVLO) and can

• Small 8-Pin SOIC (D) Package

be easily synchronized to other controllers or a

system clock to satisfy sequencing and/or noise-

APPLICATIONS

reduction requirements.

• Automotive Controls

Major sections in this data sheet include:

• Distributed Power Systems

• Specifications

• DSL/Cable Modems

• General Information

• Scanners

• Example Applications

• Telecom

• Design References

TYPICAL APPLICATION

Figure 1. 12-V to 5-V Buck Converter Figure 2. Typical Efficiency of Application Circuit 1

With 94% Efficiency (Described in Application 1)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

PAGE 1
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER Check for Samples: TPS40200-Q1 FEATURES DESCRIPTION • • • • • • • The TPS40200 is a flexible nonsynchronous controller with a built-in 200-mA driver for P-channel FETs. The circuit operates with inputs up to 52 V, with a power-saving feature that turns off driver current once the external FET has been fully turned on.
PAGE 2
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS –40°C < TA < 125°C, VDD = 12 V, fOSC = 100 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 676 696 712 mV Voltage Reference VFB Feedback voltage COMP = FB 4.5 V < VDD < 52 V –40°C < TA < 125°C Gate Driver Isrc Gate driver pullup current 125 300 Isnk Gate driver pulldown current 200 300 VGATE Gate driver output voltage 5.6 8 10 V 1.5 3.0 mA 4.25 4.
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TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com DEVICE INFORMATION TPS40200 COMP 3 FB 4 – E/A and SS Reference 8 VDD SS 2 + GDRV voltage swing limited to (VIN – 8 V) + 700 mV Soft-Start and Overcurrent PWM Logic ISNS 7 Driver 6 GDRV Enable E/A 5 GND OSC RC 1 UVLO Figure 3. Functional Block Diagram D PACKAGE (TOP VIEW) RC SS COMP FB 1 8 2 7 3 6 4 5 VDD ISNS GDRV GND Figure 4. Device Pinout TERMINAL FUNCTIONS TERMINAL NAME NO.
PAGE 5
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs VDD 3 1.66 1.65 2.5 1.64 2 1.62 IDD - mA IDD - mA 1.63 1.61 1.6 1.5 1 1.59 1.58 VDD = 12 V 0.5 1.57 0 1.56 -50 -25 0 25 50 75 100 5 125 10 15 20 25 30 35 VDD - V 40 45 50 Figure 5. Figure 6. SOFT-START THRESHOLD vs TEMPERATURE UVLO TURN ON AND TURN OFF vs TEMPERATURE 156.5 4.3 156 4.
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TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) OSCILLATOR FREQUENCY vs VDD 275 265 TJ = 25°C 20.50 260 255 Gain - dB Oscillator Frequency (kHz) 21.00 R = 68.1 kW C = 470 pF TJ = 25°C 270 POWER-STAGE GAIN vs VDD 250 245 20.00 240 235 19.50 230 225 220 19.00 5 10 15 20 25 30 35 VDD (V) 40 45 50 55 5 10 15 20 25 30 35 VDD - V 40 Figure 11. Figure 12.
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TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 TYPICAL CHARACTERISTICS (continued) MODULATOR RAMP AMPLITUDE vs VDD 6 FEEDBACK AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE 160 TJ = 25°C 140 5 120 4 IIB - nA VRAMP - V 100 3 80 60 2 40 1 20 0 0 5 10 15 20 25 30 35 VDD - V 40 45 50 55 -50 0 25 75 Figure 17. Figure 18. COMP SOURCE CURRENT vs TEMPERATURE COMP SINK CURRENT vs TEMPERATURE 100 125 100 125 3.5 3 Output Current - mA 250 200 150 100 50 2.
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TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) REFERENCE VOLTAGE vs TEMPERATURE 720 720 718 718 716 716 714 714 712 VFB - mV VFB - mV REFERENCE VOLTAGE vs TEMPERATURE VDD = 24 V 710 708 706 712 710 VDD = 4.5 V 708 706 VDD = 50 V 704 704 702 702 700 VDD = 12 V 700 -50 -25 0 25 50 75 100 125 -50 -25 0 Temp - °C 75 100 125 Figure 23. Figure 24.
PAGE 9
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 GENERAL INFORMATION Overview The TPS40200 is a nonsynchronous controller with a built-in 200-mA driver designed to drive high-speed Pchannel FETs up to 500 kHz. Its small size combined with complete functionality makes the part both versatile and easy to use. The controller uses a low-value current-sensing resistor in series with the input voltage and the power FET’s source connection to detect switching current.
PAGE 10
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com VDD VIN 8 TPS40200 + CLK RRC S Q RC RC R Q 1 Ext. Frequency Synchronization (optional) + CRC + GND 150mV 5 Figure 27. Oscillator Functional Diagram VDD VIN 8 Amplitde > VIN ¸ 10 Duty cycle < 50% TPS40200 + CLK RRC S Q RC RC R Q 1 + CRC Frequency > Controller Frequency + GND 150mV 5 Figure 28.
PAGE 11
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Current-Limit Resistor Selection As shown in Figure 31, a resistor in series with the power MOSFET sets the overcurrent protection level. Use a low-inductance resistor to avoid problems with ringing signals and nuisance tripping. When the FET is on and the controller senses 100 mV or more drop from the VDD pin to the ISNS pin, an overcurrent condition is declared.
PAGE 12
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com If necessary, a small R-C filter can be added to the current sensing network to reduce nuisance tripping due to noise pickup. This filter can also be used to trim the overcurrent trip point to a higher level with the addition of a single resistor (see Figure 31).
PAGE 13
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 MOSFET Gate Drive The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When the driver pulls the gate charge of the FET it is controlling to –8 V, the drive current folds back to a low level so that high power dissipation only occurs during the turn-on period of the FET.
PAGE 14
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Programming the Soft-Start Time An external capacitor (CSS) connected from the SS pin to ground controls the TPS40200 soft-start interval. An internal charging resistor connected to VDD produces a rising reference voltage that is connected through a 700mV offset to the reference input of the TPS40200 error amplifier. When the soft-start capacitor voltage (VCSS) is below 150 mV, there is no switching activity.
PAGE 15
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Voltage Setting and Modulator Gain Because the input current to the error amplifier is negligible, the feedback impedance can be selected over a wide range. Knowing that the reference voltage is 708 mV, pick a convenient value for R1 and then calculate the value of R2 from the following formula: æ R ö VOUT = 0.708çç1 + 2 ÷÷ R 1ø è (3) Vg L KPWM VOUT d Cout Vc Rload R2 + Vref R1 Figure 34.
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TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com EXAMPLE APPLICATIONS Application 1: Buck Regulator, 8-V to 12-V Input, 3.3-V or 5-V Output at 2.5 A Overview The buck regulator design shown in Figure 35 shows the use of the TPS40200. It delivers 2.5 A at either 3.3 V or 5 V as selected by a single feedback resistor. It achieves approximately 90% efficiency at 3.3 V and 94% at 5 V.
PAGE 17
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Component Selection Table 1. Design Parameters SYMBOL PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VIN Input voltage 8.0 12 16.0 V VOUT Output voltage IOUT at 2.5 A 3.200 3.3 3.400 (1) V Line regulation ~0.2 % VOUT 3.293 3.3 3.307 V Load regulation ~0.2% VOUT 3.293 3.3 3.307 V Output voltage IOUT at 2.5 A 4.85 5.0 5.150 (1) V Line regulation ~0.2% VOUT 4.990 5.0 5.010 V 4.990 5.0 5.
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TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Using the values in this example, the dc power loss is 129 mW.
PAGE 19
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Rectifier Selection Criteria • Rectifier breakdown voltage The rectifier must withstand the maximum input voltage, which, in this case, is 16 V. To allow for switching transients that can approach the switching voltage, a 30-V rectifier was selected. • Diode size The importance of power losses from the Schottky rectifier (D2) is determined by the duty cycle.
PAGE 20
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Inductor Selection Criteria The TPS40200 P-FET driver facilitates switching the power FET at a high frequency. This, in turn, enables the use of smaller less-expensive inductors as illustrated in this 300-kHz application. Ferrite, with its good highfrequency properties, is the material of choice.
PAGE 21
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Output Capacitance In order to satisfy the output voltage overshoot and undershoot specifications, there must be enough output capacitance to keep the output voltage within the specified voltage limits during load current steps. In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output capacitor must absorb energy stored in the output inductor.
PAGE 22
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Programming the Overcurrent Threshold Level The current limit in the TSP40200 is triggered by a comparator with a 100-mV offset whose inputs are connected across a current-sense resistor between VCC and the source of the high-side switching FET. When current in this resistor develops more than 100 mV, the comparator trips and terminates the output gate drive.
PAGE 23
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Soft-Start Capacitor The soft-start interval is given (in pF) by: C SS = t SS æ VSST ö ÷ R ´ ln çç ÷ è VSST - 1.
PAGE 24
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Frequency Compensation The four elements that determine the system overall response are discussed in this section. The gain of the error amplifier (KEA) is the first of these elements. Its output develops a control voltage that is the input to the PWM. The TPS40200 has a unique modulator that scales the peak-to-peak amplitude of the PWM ramp to be 0.1 times the value of the input voltage.
PAGE 25
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Figure 41 shows the feedback network used in this application. This is a type-2 compensation network, which gives a combination of good transient response and phase boost for good stability. This type of compensation has a pole at the origin, causing a –20-dB/decade (–1) slope, followed by a zero that causes a region of flat gain, followed by a final pole that returns the gain slope to –1.
PAGE 26
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com In order to properly compensate this system, it is necessary to know the frequencies of its poles and zeros. Step 1 The break frequency of the output capacitor is given by: Fesr = 1 2pR esr C Where: C = the output capacitor RESR = the ESR of the capacitors Because of the ESR of the output capacitor, this output filter has a single-pole response above the 1.8-kHz break frequency of the output capacitor and its ESR.
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TPS40200-Q1 www.ti.
PAGE 28
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 VOUT (S ) = VIN www.ti.com A VOL R10 R10 1+ + ´ (1 + A VOL ) R 8 ZFS Where: ZFS is the parallel combination of C7 in parallel with the sum of R8 and the impedance of C8 AVOL is the open-loop gain of the error amplifier at 35 kHz, which is 44.6 or 33 dB Figure 44 shows the result of the compensation. The crossover frequency is 35 kHz, and the phase margin is 45°.
PAGE 29
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Table 2. Bill of Materials, Buck Regulator, 12 V to 3.3 V and 5 V REF VALUE DESCRIPTION SIZE MFR PART NUMBER C1 100 μF Capacitor, Aluminum, SM, 25 V, 0.3 Ω 8 mm × 10 mm C12 220 μF Capacitor, Aluminum, SM, 6.3 V, 0.4 Ω 8 mm × 6.2 mm Panasonic EEVFC0J221P C13 100 pF Capacitor, Ceramic, 50 V, [COG], [20%] 603 muRata Std. C3 0.1 pF Capacitor, Ceramic, 50 V, [X7R], [20%] 603 muRata Std.
PAGE 30
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Figure 45. TPS40200EVM-001 Component Placement (Viewed From Top) Figure 46. TPS40200EVM001 Top Copper (Viewed From Top) Figure 47.
PAGE 31
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 Application 2: 18-V to 50-V Input, 16-V Output at 1 A This is an example of using the TPS40200 in a higher voltage application. The output voltage is 16 V at 1 A with an 18-V to 50-V input. Module boards built to this schematic and a test report are available. Test Results The efficiency and load regulation from boards built from this design are shown in Figure 49 and Figure 50. Further information and support material is available.
PAGE 32
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Application 3: Wide-Input-Voltage LED Constant-Current Driver This application uses the TPS40200 as a buck controller that drives a string of LED diodes. The feedback point for this circuit is a sense resistor in series with this string. The low 0.7-V reference minimizes power wasted in this resistor and maintains the LED current at a value given by 0.7 V/RSENSE.
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TPS40200-Q1 www.ti.
PAGE 34
TPS40200-Q1 SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 www.ti.com Layout Hints • AC current loops must be kept as short as possible. For the maximum effectiveness from C1, place it near the VDD pin of the controller and design the input ac loop consisting of C1-RSENSE-Q1-D1 to be as short as possible. Excessive high-frequency noise on VDD during switching degrades overall regulation as the load increases. • The output loop A (D1-L1-C2) should also be kept as small as possible.
PAGE 35
TPS40200-Q1 www.ti.com SLUS739E – SEPTEMBER 2006 – REVISED JULY 2013 REVISION HISTORY Changes from Revision D (July 2011) to Revision E • Page Deleted TA test condition and values from Feedback voltage parameter in ELECTRICAL CHARACTERISTICS table .....
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PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS40200QDRQ1 ACTIVE Package Type Package Pins Package Drawing Qty SOIC D 8 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-1-260C-UNLIM (4/5) -40 to 125 40200Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.