Datasheet

TPS40200-EP

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SGLS371A –JANUARY 2007–REVISED JANUARY 2013

Layout Hints

• AC current loops must be kept as short as possible. For the maximum effectiveness from C1, place it near

the VDD pin of the controller and design the input ac loop consisting of C1-R

SENSE

-Q1-D1 to be as short as

possible. Excessive high-frequency noise on VDD during switching degrades overall regulation as the load

increases.

• Output loop A (D1-L1-C2) also should be kept as small as possible. Otherwise, the application’s output noise

performance is degraded.

• It is recommended that traces carrying large ac currents NOT be connected through a ground plane. Instead,

use PCB traces on the top layer to conduct the ac current and use the ground plane as a noise shield. Split

the ground plane as necessary to keep noise away from the TPS40200 and noise-sensitive areas, such as

feedback resistors, R6 and R10.

• Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated

emissions

• For good output voltage regulation, Kelvin connections should be brought from the load to R6 and R10.

• The trace from the R6-R10 junction to the TPS40200 should be short and kept away from any noise source,

such as the SW node.

• The gate drive trace should be as close to the power FET gate as possible.

Product Folder Links: TPS40200-EP