Datasheet

mW2
2
fVC
P
S
2
MAX_INOSS
COSS
=
´´
=
mW22fVQP
SGATEGGATE
=´´=
IN
GGD
CHOFF
V
RQ
t
´
=
THIN
GGD
CHON
VV
RQ
t
-
´
=
( )
mW10tIV
2
f
t
I
V
2
f
P
CHOFFpkIN
S
CHON
pk
IN
S
SW
=´´+
÷
÷
ø
ö
ç
ç
è
æ
´´´=
( )
OUTDSONOUTIN
IRDCRVVV ´+--=D
l
S
pp
L
t
DVI ´´D=D
TPS40200-EP
www.ti.com SGLS371A –JANUARY 2007–REVISED JANUARY 2013
Where:
R
DSON
= FET on-state resistance
DCR = Inductor dc resistance
D = Duty cycle
t
S
= Reciprocal of the switching frequency
Using the values in this example, the dc power loss is 129 mW. The remaining FET losses are:
• P
SW
– Power dissipated while switching the FET on and off
• P
gate
– Power dissipated driving the FET gate capacitance
• P
COSS
– Power switching the FET output capacitance
The total power dissipated by the FET is the sum of these contributions:
P
FET
= P
SW
+ P
gate
+ P
COSS
+ P
RDSON
The P-channel FET used in this application is an FDC654P, with the following characteristics:
t
rise
= 13 × 10
–9
C
OSS
= 83 × 10
–12
t
fall
= 6 × 10
–9
Q
g
= 9 nC
R
DSON
= 0.1 Ω V
gate
= 1.9 V
Q
gd
= 1.2 × 10
–9
Q
gs
= 1.0 × 10
–9
Using these device characteristics and the following formulas produces:
(10)
Where:
and
are the switching times for the power FET.
I
G
= Q
G
× f
S
= 2.7 mA is the gate current
The sum of the switching losses is 34 mW and is comparable to the 129-mW dc losses. At added expense, a
slightly larger FET would be better because the dc loss would drop and the ac losses would increase, with both
moving toward the optimum point of equal losses.
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