Datasheet

2
1
2
pp
2
OUT
12
I
IDI
ú
ú
û
ù
ê
ê
ë
é
÷
÷
ø
ö
ç
ç
è
æ
D
+´=
rms
DSON
2
rDC
RIP ´=
ms
TPS40200-EP
SGLS371A –JANUARY 2007–REVISED JANUARY 2013 www.ti.com
Component Selection
Table 2. Design Parameters
SYMBOL PARAMETER TEST CONDITION MIN NOM MAX UNIT
V
IN
Input voltage 8 12 16 V
V
OUT
Output voltage I
OUT
at 2.5 A 3.200 3.3 3.400
(1)
V
Line regulation ±0.2% V
OUT
3.293 3.3 3.307 V
Load regulation ±0.2% V
OUT
3.293 3.3 3.307 V
V
OUT
Output voltage I
OUT
at 2.5 A 4.85 5 5.150
(1)
V
Line regulation ±0.2% V
OUT
4.990 5 5.010 V
Load regulation ±0.2% V
OUT
4.990 5 5.010 V
V
RIPPLE
Output ripple voltage At maximum output current 60 mV
V
OVER
Output overshoot For 2.5-A load transient from 2.5 A to 0.25 A 100 mV
V
UNDER
Output undershoot For 2.5-A load transient from 0.25 A to 2.5 A 60 mV
I
OUT
Output current 0.125 2.5 A
I
SCP
Short-circuit current trip point 3.75 5.00 A
At nominal input voltage and maximum output
Efficiency 90 %
current
F
S
Switching frequency 300 kHz
(1) Set-point accuracy is dependent on external resistor tolerance and the IC reference voltage. Line and load regulation values are
referenced to the nominal design output voltage.
FET Selection Criteria
• The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages that
can equal the input voltage. Since the R
DSON
of the FET rises with breakdown voltage, select a FET with as
low a breakdown voltage as possible. In this case, a 30-V FET was selected.
• The selection of a power FET’s size requires knowing both the switching losses and dc losses in the
application. AC losses are all frequency dependent and directly related to device capacitances and device
size. Conversely, dc losses are inversely related to device size. The result is an optimum where the two types
of losses are equal. Since device size is proportional to R
DSON
, a starting point is to select a device with an
R
DSON
that results in a small loss of power relative to package thermal capability and overall efficiency
objectives.
• In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss
budget of 0.916 W. Total FET losses must be small, relative to this number.
The dc conduction loss in the FET is given by:
(8)
The rms current is given by:
(9)
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