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TPS40200-EP

www.ti.com

SGLS371A –JANUARY 2007–REVISED JANUARY 2013

WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER

Check for Samples: TPS40200-EP

FEATURES

• Voltage Feed-Forward Compensation

• Undervoltage Lockout

• Controlled Baseline

• Programmable Fixed-Frequency (35 kHz to 500

– One Assembly/Test Site, One Fabrication

kHz) Operation

Site

• Programmable Short-Circuit Protection

• Extended Temperature Performance of –55°C

to 125°C

• Hiccup Overcurrent Fault Recovery

• Enhanced Diminishing Manufacturing Sources

• Programmable Closed-Loop Soft Start

(DMS) Support

• 700-mV 1% Reference Voltage

• Enhanced Product-Change Notification

• External Synchronization

• Qualification Pedigree

(1)

• Small 8-Pin Small-Outline Integrated Circuit

• Input Voltage Range 4.5 V to 52 V

(SOIC) (D) Package

• Output Voltage (700 mV to 87% V

)

APPLICATIONS

• 200-mA Internal P-Channel FET Driver

• Industrial Control

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

• Distributed Power Systems

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

• DSL/Cable Modems

temperature cycle, autoclave or unbiased HAST,

• Scanners

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

• Telecom

justifying use of this component beyond specified

performance and environmental limits.

DESCRIPTION

The TPS40200 is a flexible nonsynchronous controller with a built-in 200-mA driver for P-channel FETs. The

circuit operates with inputs up to 52 V, with a power-saving feature that turns off driver current once the external

FET has been fully turned on. This feature extends the flexibility of the device, allowing it to operate with an input

voltage up to 52 V, without dissipating excessive power. The circuit operates with voltage-mode feedback and

has feed-forward input-voltage compensation that responds instantly to input-voltage change. The integral 700-

mV reference is trimmed to 2%, providing the means to accurately control low voltages. The TPS40200 is

available in an 8-pin SOIC, and supports many of the features of more complex controllers. Clock frequency, soft

start, and overcurrent limit each are easily programmed by a single, external component. The part has

undervoltage lockout, and can be easily synchronized to other controllers or a system clock to satisfy sequencing

and/or noise-reduction requirements.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (43 pages)

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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER Check for Samples: TPS40200-EP FEATURES 1 • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Input Voltage Range 4.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 ELECTRICAL CHARACTERISTICS –55°C < TA = TJ < 125°C, VDD = 12 V, fOSC = 100 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 689 696 702 686 696 703 4.5 V < VDD < 52 V –40°C < TJ < 125°C 679 696 710 –55°C < TJ < 125°C 675 696 710 125 300 200 300 6 8 10 V 1.5 3 mA 4.25 4.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS (1) θJC Thermal resistance, junction to case θJA Thermal resistance, junction to ambient (1) θJA Thermal resistance, junction to ambient (1) (1) HIGH-K LOW-K TYP UNIT 49 °C/W 97.5 °C/W 176 °C/W TI uses test boards designed to JESD 51-3 and JESD 51-7 for thermal-impedance measurements.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 TERMINAL FUNCTIONS TERMINAL NAME I/O NO. DESCRIPTION RC 1 I Switching frequency-setting RC network. Connect capacitor from RC pin to GND pin and resistor from VIN pin to RC pin. The device may be synchronized to an external clock by connecting an open-drain output to this pin and pulling it to GND. The pulse width for synchronization should not be excessive. SS 2 I Soft-start programming pin.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) OSCILLATOR FREQUENCY vs TEMPERATURE CURRENT-LIMIT THRESHOLD vs TEMPERATURE 103 98 96 102.5 VDD = 4.5 V 102 R = 202 kW C = 470 pF 92 ILIM Threshold - mV Frequency - kHz 94 90 88 VDD = 12 V 86 84 80 -50 -25 0 25 50 75 100 101 VDD = 12 V 100.5 100 VDD = 52 V 82 101.5 99.5 -50 125 -25 0 Temperature (°C) 275 50 75 Figure 8. Figure 9.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) POWER-STAGE GAIN vs TEMPERATURE POWER-STAGE GAIN vs TEMPERATURE 20.50 20.50 20.30 20.45 VDD = 24 V VDD = 4.5 V 20.40 VDD = 12 V 19.90 Gain - dB Gain - dB 20.10 19.70 20.35 VDD = 52 V 20.30 19.50 20.25 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature - °C MODULATOR RAMP AMPLITUDE vs TEMPERATURE VDD = 24 V Vramp - V 2.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) FEEDBACK AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE MODULATOR RAMP AMPLITUDE vs VDD 6 160 TJ = 25°C 140 5 120 100 IIB - nA VRAMP - V 4 3 80 60 2 40 1 20 0 0 5 10 15 20 25 30 35 VDD - V 40 45 50 55 -50 25 50 75 Figure 16. Figure 17. COMP SOURCE CURRENT vs TEMPERATURE COMP SINK CURRENT vs TEMPERATURE 100 125 100 125 3.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) GATE DRIVE VOLTAGE vs TEMPERATURE 8.4 8 VDD = 12 V 7.8 VJ = 25°C 8.2 7.6 VGATE - V GATE DRIVE VOLTAGE vs VIN 8 7.4 7.8 7.2 7.6 7 7.4 6.8 7.2 6.6 7 6.4 Temperature - °C 30 35 VDD - V Figure 20. Figure 21.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com GENERAL INFORMATION Overview The TPS40200 is a nonsynchronous controller with a built-in 200-mA driver, designed to drive high-speed Pchannel FETS up to 500 kHz. Its small size combined with complete functionality makes the part both versatile and easy to use. The controller uses a low-value current-sensing resistor in series with the input voltage and the power FET source connection to detect switching current.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 VDD VIN 8 + CLK RRC S Q RC RC R Q 1 Ext. Frequency Synchronization (optional) + CRC + GND 150 mV 5 Figure 24. Oscillator Functional Diagram VDD VIN 8 Amplitude > VIN ¸ 10 Duty cycle < 50% + CLK RRC S Q RC RC R Q 1 + CRC Frequency > Controller Frequency + GND 150 mV 5 Figure 25.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Current-Limit Resistor Selection As shown in Figure 28, a resistor in series with the power MOSFET sets the overcurrent protection level. Use a low-inductance resistor to avoid problems with ringing signals and nuisance tripping. When the FET is on and the controller senses 100 mV or more drop from the VDD pin to the ISNS pin, an overcurrent condition is declared.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 If necessary, a small R-C filter can be added to the current-sensing network to reduce nuisance tripping due to noise pickup. This filter also can be used to trim the overcurrent trip point to a higher level with the addition of a single resistor. See Figure 28.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com MOSFET Gate Drive The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When the driver pulls the gate charge of the FET, it is controlling to –8 V, the drive current folds back to a low level so that high power dissipation only occurs during the turnon period of the FET.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Programming the Soft-Start Time An external capacitor, CSS, connected from the soft-start (SS) pin to ground controls the TPS40200 soft-start interval. An internal charging resistor connected to VDD produces a rising reference voltage, which is connected though a 700-mV offset to the reference input of the TPS40200 error amplifier. When the soft-start capacitor voltage (VCSS) is below 150 mV, there is no switching activity.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Voltage Setting and Modulator Gain Since the input current to the error amplifier is negligible, the feedback impedance can be selected over a wide range. Knowing that the reference voltage is 708 mV, pick a convenient value for R1 and then calculate the value of R2 from the following formula: æ R ö VOUT = 0.708çç1 + 2 ÷÷ R 1ø è (7) Vg L KPWM VOUT d Cout Vc Rload R2 + Vref R1 Figure 31.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 EXAMPLE APPLICATIONS Application 1: Buck Regulator, 8-V to 12-V Input, 3.3 V or 5 V at 2.5-A Output Overview The buck regulator design shown in Figure 32 illustrates the use of the TPS40200. It delivers 2.5 A at either 3.3 V or 5 V as selected by a single feedback resistor. It achieves approximately 90% efficiency at 3.3 V and 94% at 5 V.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Component Selection Table 2. Design Parameters SYMBOL PARAMETER TEST CONDITION MIN NOM MAX UNIT VIN Input voltage 8 12 16 V VOUT Output voltage IOUT at 2.5 A 3.200 3.3 3.400 (1) V Line regulation ±0.2% VOUT 3.293 3.3 3.307 V Load regulation ±0.2% VOUT 3.293 3.3 3.307 V Output voltage IOUT at 2.5 A 4.85 5 5.150 (1) V Line regulation ±0.2% VOUT 4.990 5 5.010 V 4.990 5 5.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Where: DIpp = DV ´ D ´ tS Ll DV = VIN - VOUT - (DCR + R DSON ) ´ IOUT RDSON = FET on-state resistance DCR = Inductor dc resistance D = Duty cycle tS = Reciprocal of the switching frequency Using the values in this example, the dc power loss is 129 mW.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Rectifier Selection Criteria • Rectifier breakdown voltage The rectifier has to withstand the maximum input voltage which, in this case, is 16 V. To allow for switching transients that can approach the switching voltage, a 30-V rectifier was selected. • Diode size The importance of power losses from the Schottky rectifier (D2) is determined by the duty cycle.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Inductor Selection Criteria The TPS40200 P-channel FET driver facilitates switching the power FET at a high frequency. This, in turn, enables the use of smaller, less-expensive inductors as shown in this 300-kHz application. Ferrite, with its good high-frequency properties, is the material of choice.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Output Capacitance In order to satisfy the output voltage overshoot and undershoot specifications, there must be enough output capacitance to keep the output voltage within the specified voltage limits during load current steps. In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output capacitor must absorb energy stored in the output inductor.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Switching Frequency The TPS40200 has a built-in, 8-V, 200-mA, P-channel FET driver output that facilitates using P-channel switching FETs. A clock frequency of 300 kHz was chosen as a switching frequency which represents a compromise between a high frequency that allows the use of smaller capacitors and inductors, but one that is not so high as to cause excessive transistor switching losses.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Soft-Start Capacitor The soft-start interval is given (in pF) by: t SS C SS = ´ 10 3 æ VSST ö ÷ R ´ ln çç ÷ è VSST - 1.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Frequency Compensation The four elements that determine the system overall response are discussed in the following paragraphs. The gain of the error amplifier (KEA) is the first of three elements. Its output develops a control voltage, which is the input to the PWM. The TPS40200 has a unique modulator that scales the peak-to-peak amplitude of the PWM ramp to be 0.1 times the value of the input voltage.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Figure 38 shows the feedback network used in this application. This is a type-2 compensation network, which gives a combination of good transient response and phase boost for good stability. This type of compensation has a pole at the origin, causing a –20-dB/decade (–1) slope, followed by a zero that causes a region of flat gain, followed by a final pole that returns the gain slope to –1.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 In order to properly compensate this system, it is necessary to know the frequencies of its poles and zeros. Step 1 The break frequency of the output capacitor is given by: Fesr = 1 2pR esr C (20) Where: L = 33 μH C = 221 μF Because of the ESR of the output capacitor, this output filter has a single-pole response above the 1.8-kHz break frequency of the output capacitor and its ESR.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 50 180 40 160 30 140 120 Gain GAIN 10 100 0 -10 80 Phase 60 -20 40 -30 20 -40 -50 0.1 PHASE - DEGREES 20 1 10 100 0 1000 CROSSOVER FREQUENCY - kHz Figure 40. Overall System Gain and Phase Response Figure 40 also shows the phase boost that gives the system a crossover phase margin of 47°. The Bill of Materials (BOM) for this application is given in Table 3.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Table 3. Bill of Materials, Buck Regulator, 12 V to 3.3 V and 5 V REF. DES. VALUE DESCRIPTION SIZE MFR. PART NUMBER C1 100 μF Capacitor, Aluminum, SM, 25-V, 0.3 Ω 8 x 10 mm Sanyo 20SVP100M C12 220 μF Capacitor, Aluminum, SM, 6.3-V, 0.4 Ω 8 x 6.2 mm Panasonic EEVFC0J221P C13 100 pF Capacitor, Ceramic, 50V, [COG], [20%] 603 muRata Std. C3 0.1 pF Capacitor, Ceramic, 50V, [X7R], [20%] 603 muRata Std.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Figure 41. TPS40200EVM-001 Component Placement (Viewed From Top) Figure 42. TPS40200EVM001 Top Copper (Viewed From Top) Figure 43.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com Application 2: 18-V to 50-V Input, 16 V at 1-A Output This is an example of using the TPS40200 in a higher-voltage application. The output voltage is 16 V at 1 A, with an 18-V to 50-V input. Module boards built to this schematic, and a test report, are available from the factory. The following shows some of the test results. Test Results Figure 45 and Figure 46 show some of the performance obtained from this application.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Application 3: Wide Input Voltage LED Constant-Current Driver This application uses the TPS40200 as a buck controller that drives a string of LED diodes. The feedback point for this circuit is a sense resistor in series with this string. The low 0.7-V reference minimizes power wasted in this resistor, and maintains the LED current at a value given by 0.7/RSENSE.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.
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TPS40200-EP www.ti.com SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 Layout Hints • AC current loops must be kept as short as possible. For the maximum effectiveness from C1, place it near the VDD pin of the controller and design the input ac loop consisting of C1-RSENSE-Q1-D1 to be as short as possible. Excessive high-frequency noise on VDD during switching degrades overall regulation as the load increases. • Output loop A (D1-L1-C2) also should be kept as small as possible.
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TPS40200-EP SGLS371A – JANUARY 2007 – REVISED JANUARY 2013 www.ti.com The TPS40200 is encapsulated in a standard plastic SOIC-8 package. The typical PC-board layout for this package is shown in Figure 50. 3.81 3 5.2 7.4 2.2 1.27 0.6 Dimensions are in millimeters Figure 50.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS40200MDREP Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40200MDREP SOIC D 8 2500 367.0 367.0 35.
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