Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers SOIC 8

HKQ as formed or HKJ mounted dead bu

COMP

VDD

ISNS

GDRV

GND

COMP

VDD

ISNS

GDRV

GND

TPS40200-HT

www.ti.com

SGLS400C –OCTOBER 2009–REVISED DECEMBER 2012

WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER

Check for Samples: TPS40200-HT

FEATURES

SUPPORTS EXTREME TEMPERATURE

APPLICATIONS

• Input Voltage Range 5.5 V to 52 V

• Controlled Baseline

• Output Voltage (700 mV to 87% V

)

• One Assembly/Test Site

• 200-mA Internal P-Channel FET Driver

• One Fabrication Site

• Voltage Feed-Forward Compensation

• Available in Extreme (–55°C/210°C)

• Undervoltage Lockout

Temperature Range

(1)

• Programmable Fixed-Frequency

• Extended Product Life Cycle

(35 kHz to 500 kHz) Operation

• Extended Product-Change Notification

• Programmable Short-Circuit Protection

• Product Traceability

• Hiccup Overcurrent Fault Recovery

• Texas Instruments high temperature products

• Programmable Closed-Loop Soft Start

utilize highly optimized silicon (die) solutions

• 700-mV 1% Reference Voltage

with design and process enhancements to

• External Synchronization

maximize performance over extended

temperatures.

APPLICATIONS

• Down-Hole Drilling

• High Temperature Environments (1) Custom temperature ranges available

D OR HKJ PACKAGE HKQ PACKAGE

(TOP VIEW) (TOP VIEW)

DESCRIPTION

The TPS40200 is a flexible nonsynchronous controller with a built-in 200-mA driver for P-channel FETs. The

circuit operates with inputs up to 52 V, with a power-saving feature that turns off driver current once the external

FET has been fully turned on. This feature extends the flexibility of the device, allowing it to operate with an input

voltage up to 52 V, without dissipating excessive power. The circuit operates with voltage-mode feedback and

has feed-forward input-voltage compensation that responds instantly to input-voltage change. The integral 700-

mV reference is trimmed to 2%, providing the means to accurately control low voltages. Clock frequency, soft

start, and overcurrent limit each are easily programmed by a single, external component. The part has

undervoltage lockout, and can be easily synchronized to other controllers or a system clock to satisfy sequencing

and/or noise-reduction requirements.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (46 pages)

PAGE 1
TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 WIDE-INPUT-RANGE NONSYNCHRONOUS VOLTAGE-MODE CONTROLLER Check for Samples: TPS40200-HT FEATURES 1 • • • • • • • • • • • Input Voltage Range 5.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Table 1. Bond Pad Coordinates in Microns DISCRIPTION PAD NUMBER X min Y min X max Y max RC 1 63.27 1124.01 164.07 1224.81 SS 2 61.20 922.77 162.00 1023.57 COMP 3 61.20 250.38 162.00 351.18 FB 4 70.20 74.16 171.00 174.96 GND 5 1193.94 91.44 1294.74 192.24 GDRV 6 1188.90 245.34 1289.70 346.14 ISNS 7 1189.80 978.30 1290.60 1079.10 VDD 8 1137.60 1148.49 1238.40 1249.29 Table 2.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com ELECTROSTATIC DISCHARGE (ESD) PROTECTION MAX UNIT Human-Body Model MIN 1000 V CDM 1500 V ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT VDD Input voltage range 52 RC, FB –0.3 to 5.5 SS Output voltage range V –0.3 to 9 ISNS, COMP –0.
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TPS40200-HT www.ti.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PACKAGE PARAMETER θJC D HKJ or HKQ θJC MIN Junction-to-case thermal resistance TYP MAX 49 Junction-to-case thermal resistance (to bottom of case) °C/W 5.7 Junction-to-case thermal resistance (to top of case lid - as if formed dead bug) UNIT 13.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 DEVICE INFORMATION Figure 4. Functional Block Diagram COMP 3 FB 4 – E/A and SS Reference 8 VDD SS 2 + GDRV voltage swing limited to (VIN – 8 V) + 700 mV Soft-Start and Overcurrent PWM Logic ISNS 7 Driver 6 GDRV Enable E/A 5 GND OSC RC 1 UVLO TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION RC 1 I Switching frequency-setting RC network. Connect capacitor from RC pin to GND pin and resistor from VIN pin to RC pin.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs TEMPERATURE (VDD = 12 V) QUIESCENT CURRENT vs VDD 3 1.67 1.66 2.5 1.65 1.64 2 I+ (mA) ID D (m A ) 1.63 1.62 1.61 1.5 1.6 1 1.59 1.58 0.5 1.57 1.56 0 -65 -40 -15 10 35 60 5 85 110 135 160 185 210 10 15 20 25 40 45 Figure 6. SOFT-START THRESHOLD vs TEMPERATURE (VDD = 12 V) UVLO TURNON AND TURNOFF vs TEMPERATURE 50 55 5 157 156.5 156 155.5 155 154.5 154 153.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) CURRENT-LIMIT THRESHOLD vs TEMPERATURE (VDD = 12 V) OSCILLATOR FREQUENCY vs TEMPERATURE 110 110 R = 202 kW C = 470 pF 108 VDD=5.5V IL IM Threshold (m V ) F re q u e n c y (k H z ) 105 100 VDD=12V 95 90 VDD=52V 85 106 104 102 100 80 -65 -40 -15 10 98 35 60 -65 -40 -15 85 110 135 160 185 210 10 35 Temperature(°C) 85 110 135 160 185 210 Figure 9. Figure 10.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) POWER-STAGE GAIN vs TEMPERATURE POWER-STAGE GAIN vs TEMPERATURE 22 22 21.5 21.5 21 21 G a in (d B ) G a in (d B ) VDD =52 V 20.5 VDD =12 V 20 19.5 19 20 19.5 19 VDD =5.5 V 18.5 18.5 18 18 -65 -40 -15 10 35 60 85 110 135 160 185 210 -65 -40 -15 35 60 85 110 135 160 185 210 Temperature (°C) Figure 13. Figure 14.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) FEEDBACK AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE (VDD = 12 V) MODULATOR RAMP AMPLITUDE vs VDD 1300 6 1200 TJ = 25°C 1100 5 1000 900 800 IB (mA) VRAMP (V) 4 3 700 600 500 2 400 300 1 200 100 0 0 10 15 20 25 30 35 VDD (V) 40 45 50 55 -65 -40 -15 10 35 60 85 110 135 160 185 210 Temperature (°C) Figure 17. Figure 18.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) GATE DRIVE VOLTAGE vs VDD 8 7.8 7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 8.4 VJ = 25°C 8.2 8 VGATE (V) V G A T E (V ) GATE DRIVE VOLTAGE vs TEMPERATURE (VDD = 12 V) 7.8 7.6 7.4 7.2 7 -65 -40 -15 10 35 60 85 5 110 135 160 185 210 10 15 20 25 Temperature (°C) 30 35 VDD (V) 40 Figure 21. Figure 22.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 GENERAL INFORMATION Overview The TPS40200 is a nonsynchronous controller with a built-in 200-mA driver, designed to drive high-speed Pchannel FETS up to 500 kHz. Its small size combined with complete functionality makes the part both versatile and easy to use. The controller uses a low-value current-sensing resistor in series with the input voltage and the power FET source connection to detect switching current.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 VDD VIN www.ti.com 8 + CLK RRC S Q RC RC R Q 1 Ext. Frequency Synchronization (optional) + CRC + GND 150 mV 5 Figure 25. Oscillator Functional Diagram VDD VIN 8 Amplitude > VIN ¸ 10 Duty cycle < 50% + CLK RRC S Q RC RC R Q 1 + CRC Frequency > Controller Frequency + GND 150 mV 5 Figure 26.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Current-Limit Resistor Selection As shown in Figure 29, a resistor in series with the power MOSFET sets the overcurrent protection level. Use a low-inductance resistor to avoid problems with ringing signals and nuisance tripping. When the FET is on and the controller senses 100 mV or more drop from the VDD pin to theISNS pin, an overcurrent condition is declared.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com If necessary, a small R-C filter can be added to the current-sensing network to reduce nuisance tripping due to noise pickup. This filter also can be used to trim the overcurrent trip point to a higher level with the addition of a single resistor. See Figure 29.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 MOSFET Gate Drive The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When the driver pulls the gate charge of the FET, it is controlling to –8 V, the drive current folds back to a low level so that high power dissipation only occurs during the turnon period of the FET.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Programming the Soft-Start Time An external capacitor, CSS, connected from the soft-start (SS) pin to ground controls the TPS40200 soft-start interval. An internal charging resistor connected to VDD produces a rising reference voltage, which is connected though a 700-mV offset to the reference input of the TPS40200 error amplifier. When the soft-start capacitor voltage (VCSS) is below 150 mV, there is no switching activity.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Voltage Setting and Modulator Gain Since the input current to the error amplifier is negligible, the feedback impedance can be selected over a wide range. Knowing that the reference voltage is 708 mV, pick a convenient value for R1 and then calculate the value of R2 from the following formula: æ R ö VOUT = 0.708çç1 + 2 ÷÷ R 1ø è (7) Vg L KPWM VOUT d Cout Vc Rload R2 + Vref R1 Figure 32.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com EXAMPLE APPLICATIONS Application 1: Buck Regulator, 8-V to 12-V Input, 3.3 V or 5 V at 2.5-A Output Overview The buck regulator design shown in Figure 33 illustrates the use of the TPS40200. It delivers 2.5 A at either 3.3 V or 5 V as selected by a single feedback resistor. It achieves approximately 90% efficiency at 3.3 V and 94% at 5 V.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Component Selection Table 4. Design Parameters SYMBOL PARAMETER TEST CONDITION MIN NOM MAX UNIT VIN Input voltage 8 12 16 V VOUT Output voltage IOUT at 2.5 A 3.200 3.3 3.400 (1) V Line regulation ±0.2% VOUT 3.293 3.3 3.307 V Load regulation ±0.2% VOUT 3.293 3.3 3.307 V Output voltage IOUT at 2.5 A 4.85 5 5.150 (1) V Line regulation ±0.2% VOUT 4.990 5 5.010 V 4.990 5 5.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Where: DIpp = DV ´ D ´ tS Ll DV = VIN - VOUT - (DCR + R DSON ) ´ IOUT RDSON = FET on-state resistance DCR = Inductor dc resistance D = Duty cycle tS = Reciprocal of the switching frequency Using the values in this example, the dc power loss is 129 mW.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Rectifier Selection Criteria • Rectifier breakdown voltage The rectifier has to withstand the maximum input voltage which, in this case, is 16 V. To allow for switching transients that can approach the switching voltage, a 30-V rectifier was selected. • Diode size The importance of power losses from the Schottky rectifier (D2) is determined by the duty cycle.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Inductor Selection Criteria The TPS40200 P-channel FET driver facilitates switching the power FET at a high frequency. This, in turn, enables the use of smaller, less-expensive inductors as shown in this 300-kHz application. Ferrite, with its good high-frequency properties, is the material of choice.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Output Capacitance In order to satisfy the output voltage overshoot and undershoot specifications, there must be enough output capacitance to keep the output voltage within the specified voltage limits during load current steps. In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output capacitor must absorb energy stored in the output inductor.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Switching Frequency The TPS40200 has a built-in, 8-V, 200-mA, P-channel FET driver output that facilitates using P-channel switching FETs. A clock frequency of 300 kHz was chosen as a switching frequency which represents a compromise between a high frequency that allows the use of smaller capacitors and inductors, but one that is not so high as to cause excessive transistor switching losses.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Soft-Start Capacitor The soft-start interval is given (in pF) by: t SS C SS = ´ 10 3 æ VSST ö ÷ R ´ ln çç ÷ è VSST - 1.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Frequency Compensation The four elements that determine the system overall response are discussed in the following paragraphs. The gain of the error amplifier (KEA) is the first of three elements. Its output develops a control voltage, which is the input to the PWM. The TPS40200 has a unique modulator that scales the peak-to-peak amplitude of the PWM ramp to be 0.1 times the value of the input voltage.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Figure 39 shows the feedback network used in this application. This is a type-2 compensation network, which gives a combination of good transient response and phase boost for good stability. This type of compensation has a pole at the origin, causing a –20-dB/decade (–1) slope, followed by a zero that causes a region of flat gain, followed by a final pole that returns the gain slope to –1.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com In order to properly compensate this system, it is necessary to know the frequencies of its poles and zeros. Step 1 The break frequency of the output capacitor is given by: 1 2pR esr C Fesr = (20) Where: L = 33 μH C = 221 μF Because of the ESR of the output capacitor, this output filter has a single-pole response above the 1.8-kHz break frequency of the output capacitor and its ESR.
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TPS40200-HT www.ti.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com 50 180 40 160 30 140 120 Gain GAIN 10 100 0 -10 80 Phase 60 -20 40 -30 20 -40 -50 0.1 PHASE - DEGREES 20 1 10 100 0 1000 CROSSOVER FREQUENCY - kHz Figure 41. Overall System Gain and Phase Response Figure 41 also shows the phase boost that gives the system a crossover phase margin of 47°. The Bill of Materials (BOM) for this application is given in Table 5.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Table 5. Bill of Materials, Buck Regulator, 12 V to 3.3 V and 5 V REF. DES. VALUE DESCRIPTION SIZE MFR. PART NUMBER C1 100 μF Capacitor, Aluminum, SM, 25 V, 0.3 Ω 8 x 10 mm Sanyo 20SVP100M C12 220 μF Capacitor, Aluminum, SM, 6.3 V, 0.4 Ω 8 x 6.2 mm Panasonic EEVFC0J221P C13 100 pF Capacitor, Ceramic, 50 V, [COG], [20%] 603 muRata Std. C3 0.1 pF Capacitor, Ceramic, 50 V, [X7R], [20%] 603 muRata Std.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Figure 42. TPS40200EVM-001 Component Placement (Viewed From Top) Figure 43. TPS40200EVM001 Top Copper (Viewed From Top) Figure 44.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 Application 2: 18-V to 50-V Input, 16 V at 1-A Output This is an example of using the TPS40200 in a higher-voltage application. The output voltage is 16 V at 1 A, with an 18-V to 50-V input. Module boards built to this schematic, and a test report, are available from the factory. The following shows some of the test results. Test Results Figure 46 and Figure 47 show some of the performance obtained from this application.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Application 3: Wide Input Voltage LED Constant-Current Driver This application uses the TPS40200 as a buck controller that drives a string of LED diodes. The feedback point for this circuit is a sense resistor in series with this string. The low 0.7-V reference minimizes power wasted in this resistor, and maintains the LED current at a value given by 0.7/RSENSE.
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TPS40200-HT www.ti.
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TPS40200-HT SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 www.ti.com Layout Hints • AC current loops must be kept as short as possible. For the maximum effectiveness from C1, place it near the VDD pin of the controller and design the input ac loop consisting of C1-RSENSE-Q1-D1 to be as short as possible. Excessive high-frequency noise on VDD during switching degrades overall regulation as the load increases. • Output loop A (D1-L1-C2) also should be kept as small as possible.
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TPS40200-HT www.ti.com SGLS400C – OCTOBER 2009 – REVISED DECEMBER 2012 The TPS40200 is encapsulated in a standard plastic SOIC-8 package. The typical PC-board layout for this package is shown in Figure 51. 3.81 3 5.2 7.4 2.2 1.27 0.6 Dimensions are in millimeters Figure 51.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.