Datasheet

1
2
3
4
SS
COMP
FB
RC 8
7
6
5
ISNS
GDRV
GND
VDD
SS COMP FBRC
8 57 6
1 42 3
ISNS GDRV GNDVDD
TPS40200
www.ti.com SLUS659F –FEBRUARY 2006–REVISED MARCH 2012
Table 2.
TERMINAL
I/O DESCRIPTION
NAME NO.
COMP 3 O Error amplifier output. Connect control loop compensation network from COMP to FB.
FB 4 I Error amplifier inverting input. Connect feedback resistor network center tap to this pin.
GND 5 Device ground.
GDRV 6 O Driver output for external P-channel MOSFET
Current-sense comparator input. Connect a current sense resistor between ISNS and VDD in order to set
ISNS 7 I
desired overcurrent threshold.
Switching frequency setting RC network. Connect a capacitor from the RC pin to the GND pin and connect a
resistor from the VDD pin to the RC pin. The device may be synchronized to an external clock by connecting
RC 1 I
an open drain output to this pin and pulling it to GND. For mor info on pulse width for synchronization,
please refer to the Synchronizing the Oscillator section.
Soft-start programming pin. Connect capacitor from SS to GND to program soft start time. Pulling this pin
SS 2 I below 150 mV causes the output switching to stop, placing the device in a shutdown state. The pin also
functions as a restart timer for overcurrent events.
VDD 8 I System input voltage. Connect local bypass capacitor from VDD to GND.
QFN (DRB) PACKAGE
SOIC (D) PACKAGE
BOTTOM VIEW)
(TOP VIEW)
Copyright © 2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS40200