Datasheet
TPS40200
www.ti.com
SLUS659F –FEBRUARY 2006–REVISED MARCH 2012
Layout Hints
• Keep the ac current loops as short as possible. For the maximum effectiveness from C3, place it near the
VDD pin of the controller and design the input ac loop consisting of C1-R
SENSE
-Q1-D1 to be as short as
possible. Excessive high frequency noise on VDD during switching degrades overall regulation as the load
increases.
• Keep the output loop A (D1-L1-C2) as small as possible. A larger loop can degrade the application output
noise performance.
• Traces carrying large ac currents should NOT be connected through a ground plane. Instead, use PCB traces
on the top layer to conduct the ac current and use the ground plane as a noise shield. Split the ground plane
as necessary to keep noise away from the TPS40200 and noise sensitive areas such as feedback resistors
R6, and R10.
• Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated
emissions
• For good output voltage regulation, Kelvin connections should be brought from the load to R6 and R10.
• The trace from the R6-R10 junction to the TPS40200 should be short and kept away from any noise source
(such as the SW node).
• The gate drive trace should be as close as possible. to the power FET gate
Related Devices
DEVICE NUMBER DESCRIPTION
TPS4007
Low Input Synchronous Buck Controller
TPS4009
TL5001 Wide Input Range Controller
TPS40057 Wide input (8V to 40V) Synchronous Buck Controller
TPS40190 Low Pin Count Synchronous Buck Controller
TPS40192
– 4.5 V to 18 V Low Pin Count Synchronous Buck Controller
TPS40193
Reference Documents
• Under the Hood of Low Voltage DC/DC Converters – SEM1500 Topic 5 – 2002 Seminar Series
• Understanding Buck Power Stages in Switchmode Power Supplies – SLVA057 - March 1999
• Design and Application Guide for High Speed MOSFET Gate Drive Circuits- SEM 1400 – 2001 Seminar
Series
• Designing Stable Control Loops - SEM 1400 – 2001 Seminar Series
• http://power.ti.com
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