Datasheet

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2
O
2
OSO
2
OO
VVC
2
1
IL
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OFFMAX
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C
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TPS40200
SLUS659F –FEBRUARY 2006–REVISED MARCH 2012 www.ti.com
Output Capacitance
In order to satisfy the output voltage over and under shoot specifications there must be enough output
capacitance to keep the output voltage within the specified voltage limits during load current steps.
In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output
capacitor must absorb energy stored in the output inductor. This condition may be described by realizing that the
energy in the stored in the inductor must be suddenly absorbed by the output capacitance. This energy
relationship is written as:
where
• V
OS
is the allowed over-shoot voltage above the output
voltage
• L
O
is the inductance
• I
O
is the output current
• C
O
is the output capacitance
• V
O
is the output voltage
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In this application, the worst case load step is 2.25 A and the allowed overshoot is 100 mV. With a 33-μH output
inductor, this implies an output capacitance of 249 μF for a 3.3-V output and 165 μF for a 5-V output..
When the load increases from minimum to full load the output capacitor must deliver current to the load. The
worst case is for a minimum on time that occurs at 16 V in and 3.3 V
OUT
and minimum load. This corresponds to
an off time of (1 – 0.2 ) times the period 3.3-μs and is the worst case time before the inductor can start supplying
current. This situation may be represented by
where
• ΔV
O
is the undershoot specification of 60 mV
• ΔI
O
is the load current step
• t
OFF(max)
is the maximum off time
This condition produces a requirement of 100 μF for the output capacitance. The larger of these two
requirements becomes the minimum value of output capacitance.
The ripple current develops a voltage across the ESR of the output capacitance, so another requirement on this
component is it ESR be small relative to the ripple voltage specification.
Switching Frequency
The TPS40200 has a built in, 8-V, 200 mA, P-channel FET driver output that facilitates using P-channel switching
FETs A clock frequency of 300 kHz is chosen as a switching frequency that represents a compromise between a
high-frequency that allows the use of smaller capacitors and inductors but one that is not so high as to cause
excessive transistor switching losses. As previously discussed, an optimum frequency can be selected by picking
a value where the dc and switching losses are equal.
The frequency is set by using the design formula given in the FET Selection Criteria section.
where
• R
RC
is the timing resistor value in Ω
• R
RC
= 68.1 kΩ
• C
RC
is the timing capacitor value in F
• C5 = 470 pF
• f
SW
is the desired switching frequency in Hz
• f
SW
= 297 kHz.
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