Datasheet

= + + +
FET SW GATE COSS RDS(on)
P P P P P
( )
mW10tIV
2
f
t
I
V
2
f
P
CHOFFpkIN
S
CHON
pk
IN
S
SW
=´´+
÷
÷
ø
ö
ç
ç
è
æ
´´´=
( )
´
=
-
GD G
CH on
IN TH
Q R
t
V V
( )
´
=
GD G
CH off
IN
Q R
t
V
mW22fVQP
SGATEGGATE
=´´=
mW2
2
fVC
P
S
2
MAX_INOSS
COSS
=
´´
=
TPS40200
www.ti.com SLUS659F –FEBRUARY 2006–REVISED MARCH 2012
Using the values in this example, the dc power loss is 129 mW. The remaining FET losses are as follows:
• P
SW
is the power dissipated while switching the FET on and off
• P
gate
is the power dissipated driving the FET gate capacitance
• P
COSS
is the power switching the FET output capacitance
The total power dissipated by the FET is the sum of these contributions.
(8)
The P-channel FET used in this application is a FDC654P with the following characteristics:
t
RISE
= 13 × 10
–9
C
OSS
= 83 × 10
–12
t
FALL
= 6 × 10
–9
Q
g
= 9 nC
R
DS(on)
= 0.1 Ω V
GATE
= 1.9 V
Q
gd
= 1.2 × 10
–9
Q
gs
= 1.0 × 10
–9
Using these device characteristics and Equation 9:
(9)
where and are the switching times for the power FET.
(10)
(11)
The gate current, I
G
= Q
G
× f
S
= 2.7 mA
The sum of the switching losses is 34 mW, and is comparable to the 129 mW dc losses. At added expense, a
slightly larger FET is better because the dc loss drops and the ac losses increase, with both moving toward the
optimum point of equal losses.
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