Datasheet

DSON
2
rDC
RIP ´=
ms
-
D = D ´ ´
S
P P
I
t
I V D
L
( )
-
æ ö
æ ö
D
ç ÷
ç ÷
= ´ +
ç ÷
ç ÷
ç ÷
è ø
è ø
1
2
2
P P
2
RMS OUT
I
I D I
12
( )
OUTDSONOUTIN
IRDCRVVV ´+--=D
TPS40200
SLUS659F –FEBRUARY 2006–REVISED MARCH 2012 www.ti.com
Component Selection
Table 3. Design Parameters
PARAMETER TEST CONDITION MIN NOM MAX UNIT
V
IN
Input Voltage 8 12 16 V
V
OUT
Output Voltage I
OUT
= 2.5 A 3.2 3.3 3.4
(1)
V
Line Regulation ± 0.2 % V
OUT
3.293 3.300 3.307 V
Load Regulation ± 0.2% V
OUT
3.293 3.300 3.307 V
V
OUT
Output Voltage I
OUT
at 2.5 A 4.85 5.0 5.150
(1)
V
Line Regulation ± 0.2% × V
OUT
4.99 5.00 5.01 V
Load Regulation ± 0.2% × V
OUT
4.99 5.00 5.01 V
V
RIPPLE
Output ripple voltage At maximum output current 60 mV
V
OVER
Output overshoot For 2.5 A load transient from 2.5 A to 0.25 A 100 mV
V
UNDER
Output undershoot For 2.5 A load transient from 0.25 A to 2.5 A 60 mV
I
OUT
Output Current 0.125 2.500 A
I
SCP
Short circuit current trip point 3.75 5.00 A
Efficiency At nominal input voltage and maximum 90%
output current
F
S
Switching frequency 300 kHz
(1) Set point accuracy is dependent on external resistor tolerance and the device reference voltage. Line and Load regulation values are
referenced to the nominal design output voltage.
FET Selection Criteria
• The maximum input voltage for this application is 16 V. Switching the inductor causes overshoot voltages that
can equal the input voltage. Since the R
DS(on)
of the FET rises with breakdown voltage, select a FET with as
low a breakdown voltage as possible. In this case, a 30-V FET was selected.
• The selection of a power FET size requires knowing both the switching losses and dc losses in the
application. ac losses are all frequency dependent and directly related to device capacitances and device
size. On the other hand, dc losses are inversely related to device size. The result is an optimum where the
two types of losses are equal. Since device size is proportional to R
DS(on)
, begin by selecting a device with an
R
DS(on)
that results in a small loss of power relative to package thermal capability and overall efficiency
objectives.
• In this application, the efficiency target is 90% and the output power 8.25 W. This gives a total power-loss
budget of 0.916 W. Total FET losses must be small relative to this number.
The dc conduction loss in the FET is given by:
The RMS current is given by:
where
•
•
• R
DS(on)
is the FET on-state resistance
• DCR is the the inductor dc resistance
• D is the duty cycle
• t
S
= the reciprocal of the switching frequency
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