Datasheet

−60
−30
−10
0
10
30
−50
100 1 k 10 k 1 M100 k
−40
−20
20
Double
Pole
L−C Slope
−40 dB/decade
f − Frequency − Hz
Gain − dB
ESR_Zero
OUT
1
f 318 k Hz
2 ESR C
= =
p ´ ´
f
LC_Pole
OUT OUT
1
5.8k Hz
2 L C
= =
p ´ ´
IN
RAMP
V
DCgain 20 LOG 20 LOG(12) 21.6 dB
V
æ ö
= ´ = ´ =
ç ÷
è ø
( )
( )
OUT
IN
e PWM LC
2
RAMP
OUT
OUT OUT
OUT
1 s ESR C
V
G (s) K K
V
L
1 s s L C
R
+ ´ ´
= ´ = ´
æ ö
+ ´ + ´ ´
ç ÷
è ø
( )
( )
OUT
LC
2
OUT
OUT OUT
OUT
1 s ESR C
K
L
1 s s L C
R
+ ´ ´
=
æ ö
+ ´ + ´ ´
ç ÷
è ø
TPS40195
www.ti.com SLUS720E –FEBRUARY 2007–REVISED JULY 2012
The gain of the output LC filter is given in Equation 38.
(38)
The equation for the PWM and LC gain is:
(39)
To plot this on a Bode plot the DC gain must be expressed in dB. The DC gain is equal to K
PWM
. To express this
in dB we take its LOG and multiple by 20. For this converter the DC gain is:
(40)
Also the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is
associated with the ESR of the output capacitance. The frequency at where these occur can be calculated using
Equation 41.
(41)
(42)
A Bode plot of the PWM and LC filter is shown in Figure 25.
Figure 25. PWM and L-C Filter Gain
A Type-III compensation network, shown in Figure 26, is used for this design. A typical bode plot of a Type-III
compensation network is shown below in Figure 27.
Copyright © 2007–2012, Texas Instruments Incorporated 27