Datasheet

f
DAC
SS
SW
N
1024
t 0.591 0.591 2.0 ms
300
= ´ = ´ =
( ) ( )
6 6
START
t 6.28 2.5 10 300 10 0.172ms
- -
³ ´ ´ ´ ´ =
START OUT OUT
t 2 L C³ p ´ ´
( )
UVLO
UVLO2 UVLO1
ON UVLO
V
1.26
R R 192.3 k 42.2k
7 1.26
V V
= ´ = W ´ = W
-
-
( )
ON OFF
UVLO1
6
UVLO
V V
7 6
R 192.3k
I
5.2 10
-
-
-
= = = W
´
( ) ( )
f
7 7
T
S
2.5 10 2.5 10
R 83.3 k
300
´ ´
= = = W
TPS40195
www.ti.com
SLUS720E FEBRUARY 2007REVISED JULY 2012
Using the parameters from its data sheet the actual expected power losses were calculated. Conduction loss is
0.394 W, body diode loss is 0.210 W and the gate loss was 0.063 W. This totals 0.667 W associated with the
rectifier MOSFET.
The ratio between C
gs
and C
gd
should be greater than one. The Si7886 capacitor meets this criterion and helps
reduce the risk of dv/dt induced turn on of the rectifier MOSFET. If this is likely to be a problem a small resistor
may be added in series with the boost capacitor, C
BOOST
. to slow the turn on speed of Q
SW
at the expense of
increased switching losses in that device.
Component Selection for the TPS40195
Timing Resistor, R
T
The timing resistor is calculated using the following equation.
(26)
A standard value resistor of 82.5 k is used.
Setting UVLO
The equations below are used to set the UVLO voltages.
(27)
(28)
The UVLO threshold voltage ( V
UVLO
) is 1.26 V. The module has a turn on voltage of 7 V and a turn off voltage of
6 V. This sets R
UVLO1
to 191 k, the nearest standard value. The second resistor R
UVLO2
is 42.2 k.
Setting the Soft-Start Time
The selection of the soft start time should be greater than the time constant of the output filter, L
OUT
and C
OUT
.
This time is given in Equation 29 and Equation 30.
(29)
(30)
The soft-start time is determined using Equation 31 . The TPS40195 uses a counter operating at the clock
frequency that increments an internal DAC until it reaches the turn on threshold voltage of 0.591 V. The number
of counts required to reach this threshold is determined by one of three settings on the SS pin. In this case, the
pin is floating (with a small bypass capacitor) which sets the clock count (N
DAC
) to 1024 and the soft-start time is
2.0 ms
(31)
Copyright © 2007–2012, Texas Instruments Incorporated 25