Datasheet

( )
f
BD f OUT 1 2 S
P V I t t= ´ ´ + ´
f
GATE g(TOT) g SW
P Q V= ´ ´
( )
( )
( )
2
2
2
RIPPLE
OUT
CON DS(on) QSW(rms) DS(on) OUT
IN
I
V
P R I R I
V 12
æ ö
ç ÷
= ´ = ´ ´ +
ç ÷
è ø
QSR CON BD GATE
P P P P= + +
( )
f
RIPPLE
OUT gs1 gd
SW IN S
g
I
I Q Q
2
P V
I
é ù
æ ö
+ ´ +
ê ú
ç ÷
è ø
ê ú
= ´ ´
ê ú
ê ú
ë û
( )
( )
( )
2
2
2
RIPPLE
OUT
CON DS(on) QSW(rms) DS(on) OUT
IN
I
V
P R I R I
V 12
æ ö
ç ÷
= ´ = ´ ´ +
ç ÷
è ø
TPS40195
SLUS720E –FEBRUARY 2007–REVISED JULY 2012 www.ti.com
(20)
where
• P
CON
is conduction losses
• P
SW
is switching losses
• P
GATE
is gate drive losses
• Q
gd
is drain source charge or miller charge
• Q
gs1
is gate source post threshold charge
• I
g
is gate drive current
• Q
g(TOT)
is total gate charge from 0 V to the gate voltage
• V
g
is gate voltage (21)
Equation 22 and Equation 23 describe the preliminary values for R
DS(on)
and (Q
gs1
+ Q
gd
). Note output losses due
to Q
OSS
and gate losses have been ignored here. Once a MOSFET is selected these parameters can be added.
The switching MOSFET for this design should have an R
DS (on)
of less than 20 mΩ . The sum of Q
gd
and Q
gs1
should be approximately 14.8 nC. . The Vishay SI7860ADP was selected for this design. This device has an
R
DS(on)
of 9 mΩ and a (Q
gs1
+Q
gd
) of 13 nC. The estimated conduction losses are 0.135 W and the switching
losses are 0.297 W. This gives a total estimated power loss of 0.432 W versus 0.6 W for our initial boundary
condition. Note this does not include gate losses of approximately 10 mW.
Rectifier MOSFET, Q
SR
Similar criteria as used above apply to the rectifier MOSFET. One significant difference however, is that the
rectifier MOSFET switches with nearly zero voltage across its drain and source so its switching losses are nearly
zero. There are losses from the source to drain body diode that occur as it conducts during the delay before the
FET turns on. The equations used to calculate the losses in the rectifier MOSFET are shown below.
(22)
(23)
(24)
where
• P
BD
is the body diode loss
• t
1
is the body diode conduction prior to turn-on of channel (57nS)
• t
2
is the body diode conduction after turn-off of channel (14nS)
• V
f
is the body diode forward voltage (25)
Estimating the body diode losses based on a forward voltage of 1.0 V yields 0.162 W. The gate losses are
unknown at this time so assume 0.1 W gate losses. This leaves 0.338 W for conduction losses. Using this figure
a target R
DS(on)
of 4.0 mΩ was calculated. The SI7886ADP has an R
DS(on)
maximum of 4.8 mΩ and was used for
this design.
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