Datasheet

1
5
4
3
2
6
8
7
EN
FB
COMP
VDD
UVLO
RT
ILIM
GND
16
12
13
14
15
11
9
10
HDRV
SW
BOOT
LDRV
BP
SS_SEL
PGOOD
SYNC
TPS40195
CBOOT
CBP
Cout
Cin
L
CVDD
PowerGroundPlaneSignalGroundPlane
PowerComponentsSignalComponents
Vout
Vin
1.Keeptheseloopsasshortaspossible.Runoutandreturnlinesclosetogether.
2.Keeptheswitchnodeareaassmallaspossible
3.KeepSignalandPowerGroundsseparate.Connectintoageneralpowerplaneononelayer.
See
note1.
Seenote1. See
note1.
Seenote1.
Seenote2.
Seenote3. Seenote3.
Seenote1.
TPS40195
www.ti.com SLUS720E –FEBRUARY 2007–REVISED JULY 2012
Layout Suggestions
Figure 22. Layout Suggestion
• Keep the input switching current loop as small as possible.
• Place the input capacitor (C
IN
) close to the top switching FET The output loop current loop should also be
kept as small as possible.
• Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated
emissions Kelvin connections should be brought from the output to the feedback pin (FB) of the device.
• Keep analog and non-switching components away from switching components.
• The gate drive trace should be as close to the power FET’s gate as possible.
• Make a single point connection from the signal ground to power ground.
• Do not allow switching current to flow under the device.
Copyright © 2007–2012, Texas Instruments Incorporated 19