Datasheet

f
DAC
SS
SW
N
t 0.591= ´
5
R1
R2
V
IN
+
BP
UVLO
1.26 V
I
UVLO
5.2 mA (typ)
UDG-07002
UVLO
ON UVLO
V
R2 R1
V V
= ´
-
TPS40195
www.ti.com SLUS720E –FEBRUARY 2007–REVISED JULY 2012
where
• V
ON
is the desired turn on voltage of the converter
• V
OFF
is the desired turn off voltage for the converter, must be less than V
ON
• I
UVLO
is the hysteresis current generated by the device, 5.2 μA (typ)
• V
UVLO
is the UVLO pin threshold voltage, 1.26 V (typ) (3)
Figure 20. Undervoltage Lockout
Soft Start
The TPS40195 uses a digital closed loop soft start system. The soft start ramp is generated internally by a
counter and digital-to-analog converter (DAC) that ramps up the effective reference voltage to the error amplifier.
The DAC supplies a voltage to the error amp that is used as the reference until that supplied voltage becomes
greater than the 591-mV reference voltage. At that point soft-start is complete and the 591-mV reference controls
the output voltage. The ramp rate is dependent on the oscillator frequency as each step in the DAC takes one
clock cycle from the oscillator. The user can choose from three ramp rates, or DAC counter widths depending on
viewpoint, for any given switching frequency by connecting the SS_SEL pin to GND, BP pin or letting the pin
float. The possibilities are summarized in Table 2.
Table 2. Soft Start Clock Cycles
SS_SEL Connection Clock Cycles in 1-V Ramp (N
DAC
)
GND 2048
Floating 1024
BP 512
The ramp output from the soft start DAC is 1 V in amplitude. Since the soft start is closed loop and reference
voltage of the device is actually 591 mV, the actual ramp time is less than the time it takes for the SS ramp to
finish and reach 1 V. The actual soft-start time is the amount of time that it takes for the internal soft-start ramp to
reach the 591-mV reference level. The soft-start time can be found using Equation 4.
Copyright © 2007–2012, Texas Instruments Incorporated 15