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6.5 Control Loop Bode Plot
6.5.1 Low Line (V
IN
= 8V)
60
40
20
0
20
40
60
-
-
-
Gain(dB)
100
1k 10k 100k 1M
Frequency(Hz)
180
150
120
90
60
30
0
30
60
90
120
150
180
-
-
-
-
-
-
Phase( )
°
Gain
Phase
Margin
V =8V
V =1.8V
I =10A
IN
OUT
OUT
Bandwidth:46kHz
PhaseMargin:53
°
6.5.2 High Line (V
IN
= 14V)
60
40
20
0
20
40
60
-
-
-
Gain(dB)
100
1k 10k 100k 1M
Frequency(Hz)
180
150
120
90
60
30
0
30
60
90
120
150
180
-
-
-
-
-
-
Phase( )
°
Gain
Phase
Margin
V =14V
V =1.8V
I =10A
IN
OUT
OUT
Bandwidth:68kHz
PhaseMargin:45
°
7 EVM Assembly Drawings and Layout
EVM Assembly Drawings and Layout
Figure 10. TPS40193EVM-001 Gain and Phase vs Frequency
Figure 11. TPS40193EVM-001 Gain and Phase vs Frequency
Figure 12 through Figure 17 show the design of the TPS40193EVM-001 printed circuit board (PCB). The
EVM has been designed using a 4-layer, 2oz., copper-clad PCB (2.5in x 2.5in), with all components in a
1.54in x 0.76in active area on the top side and all active traces to the top and bottom layers of the board.
This configuration allows the user to easily view, probe and evaluate the TPS40193 control IC in a
practical, double-sided application. Moving components to both sides of the PCB or using additional
internal layers can offer additional size reduction for space-constrained systems.
Unless otherwise specified, these figures illustrate the view from the top side of the PCB.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing TPS40193EVM-001 PCBs.
14 Using the TPS40193EVM-001 SLUU274 – May 2007
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