Datasheet

DRC PACKAGE

(TOP VIEW)

PGD

VDD

COMP

ENABLE

6 7 8 9 10

BP5 LDRV BOOT SW HDRV

TPS40192

TPS40193

TPS40192, TPS40193

www.ti.com

SLUS719E –MARCH 2007–REVISED MAY 2013

DEVICE INFORMATION

Table 1. TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME NO.

Gate drive voltage for the high-side N-channel MOSFET. A capacitor 100 nF typical must be connected

BOOT 8 I

between this pin and SW.

Output bypass for the internal regulator. Connect at least 1μF capacitor from this pin to GND. Larger

capacitors, up to 4.7μF will improve noise performance when using a low side FET with a gate charge of

BP5 6 O 25nC or greater. Low power, low noise loads may be connected here if desired. The sum of the external

load and the gate drive requirements must not exceed 50 mA. This regulator is turned off when ENABLE is

pulled low.

COMP 3 O Output of the error amplifier.

Logic level input which starts or stops the controller from an external user command. A high-level turns the

ENABLE 1 I controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is

not used.

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal

FB 2 I

reference voltage (591 mV typical)

GND (11) - Thermal pad ground connection. Common reference for the device. Connect to the system GND.

HDRV 10 O Bootstrapped output for driving the gate of the high side N channel FET.

LDRV 7 O Output to the rectifier MOSFET gate

PGD 5 O Open drain power good output

Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high

SW 9 I

side MOSFET driver

VDD 4 I Power input to the controller

Product Folder Links: TPS40192 TPS40193