Datasheet

A
PS(fco)
+ A
MOD(dc)
* 40 LOG
ǒ
f
CO
f
RES
Ǔ
R7 +
V
FB
R8
V
OUT
* V
FB
+
2
+
3
11
Power Pad
To
PWM
R8
R10
C2
R6
C3
C1
R7
V
OUT
V
FB
UDG−06068
TPS40192, TPS40193
www.ti.com
SLUS719E MARCH 2007REVISED MAY 2013
Figure 19. Type-III Compensator Used with TPS40040/41
Feedback Divider (R7, R8)
Select R8 to be between 10 k and 100 k. For this design, select 20 k. R7 is then selected to produce the
desired output voltage when V
FB
= 0.591 V using Equation 30.
(30)
V
FB
= 0.591 V and R8 = 20 k for V
OUT
= 1.8 V, R7 = 9.78 k, so the value of 9.76 k is selected as the closest
standard value. A slightly lower nominal value increases the nominal output voltage slightly to compensate for
some trace impedance at load.
Error Amplifier Compensation (R6, R10, C1, C2, C3)
Place two zeros at 50% and 100% of the resonance frequency to boost the phase margin before resonance
frequency generates -180° of phase shift. For f
RES
= 11.7 kHz, F
Z1
= 5.8 kHz and F
Z2
= 11 kHz. Selecting the
crossover frequency (f
CO
) of the control loop between 3 times the LC filter resonance and 1/5th the switching
frequency. For most applications 1/10th the switching frequency provides a good balance between ease of
design and fast transient response.
If f
ESR
< f
CO
F
P1
= f
ESR
and F
P2
= 4 × f
CO
.
If f
ESR
> 2 × f
CO
; F
P1
= f
CO
and F
P2
= 8 × f
CO
.
For this design
f
SW
= 600 kHz,
f
RES
= 11.7 kHz
f
ESR
= 636 kHz
f
CO
= 60 kHz and since
f
ESR
> 2 × f
CO
, F
P1
= f
CO
= 60 kHz and F
P2
= 4 × f
CO
= 500 kHz.
Since f
CO
< f
ESR
the power stage gain at the desired crossover can be approximated in Equation 31.
(31)
A
PS(FCC)
= -5.4 dB, and the error amplifier gain between the poles should be should be 10
5.4 dB/20
= 1.86.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS40192 TPS40193