Datasheet

Frequency (Log Scale)
f
RES
f
ESR
0 dB
−40 dB/decade
−20 dB/decade
A
MOD
f
ESR
+
1
2p C
OUT
R
ESR
f
RES
+
1
2p L C
Ǹ
A
MOD
+
V
IN
V
RAMP(p*p)
A
MOD
+
dV
OUT
dV
COMP
+
dD
V
COMP
V
IN
+
dt
dV
RAMP
1
T
SW
V
IN
TPS40192, TPS40193
SLUS719E –MARCH 2007–REVISED MAY 2013 www.ti.com
Feedback Compensation
Modeling the Power Stage
The DC gain of the modulator is given by Equation 26.
(26)
Since the peak-to-peak ramp voltage given in the Electrical Characteristics Table is projected from the ramp
slope over a full switching period, the modulator gain can be calculated as Equation 27.
(27)
This design finds a maximum modulator gain of 14 (23.0 dB). The L-C filter applies a double pole at the
resonance frequency described in Equation 28.
(28)
For this design with a 1.0-μH inductor and 2 100-μF capacitors, the resonance frequency is approximately
11.3 kHz. At any lower frequency, the power stage has a DC gain of 23 dB and at any higher frequency the
power stage gain drops off at -40 dB per decade. The ESR zero is approximated in Equation 29.
(29)
For C
OUT
= 2, 100-μF and R
ESR
= 2.5 mΩ each, f
ESR
= 636 kHz, greater than 1/5th the switching frequency and
outside the scope of the error amplifier design. The gain of the power stage would change to -20 dB per decade
above f
ESR
. The straight line approximation the power stage gain is described in Figure 18.
Figure 18. Approximation of Power Stage Gain
The following compensation design procedure assumes f
ESR
> f
RES
. For designs using large high-ESR bulk
capacitors on the output where f
ESR
< f
RES
. Type-II compensation can be used but is not addressed in this
document.
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