Datasheet

V
CS
+ I
L(peak)
R
DS(on)
R
VDD
t
V
RVDD(max)
I
DD
+
50 mV
3 mA )
ǒ
Q
G1
, Q
G2
Ǔ
f
SW
C
BP5
+ 100 MAX
ǒ
Q
G1
, Q
G2
Ǔ
C
BOOST
+ 20 Q
G1
TPS40192, TPS40193
www.ti.com SLUS719E –MARCH 2007–REVISED MAY 2013
Boot Strap Capacitor
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
50 mV.
(22)
Based on the IRF7466 MOSFET with a gate charge of 23 nC, we calculate minimum of 460 nF of capacitance.
The next higher standard value of 470 nF is selected for the bootstrap capacitor.
NOTE
It is recommended to add a high-resistance resistor in parallel with the bootstrap
capacitor. Adding a small amount of load to the bootstrap capacitor (100 kΩ for a 100-nF
typical capacitor) creates a discharge time constant for the bootstrap voltage following a
shutdown event. This prevents the possibility of an inadvertent turn-on of the high-side
FET following shutdown via the ENABLE pin, due to leakage paths within the driver stage
which can slowly transfer the bootstrap voltage to the HDRV pin following the shutdown.
(See Figure 17)
Input Bypass Capacitor (C6)
As suggested the TPS40192/93 datasheet, select a 1.0-μF ceramic bypass capacitor for VDD.
BP5 Bypass Capacitor (C5)
The TPS40192 recommends a minimum 1.0-μF ceramic capacitance to stabilize the 5-V regulator. To limit
regulator noise to less than 10 mV, the bypass capacitor is sized by using Equation 23.
(23)
Since Q2 is larger than Q1 and Q2's total gate charge is 44 nC, a BP5 capacitor of 4.4-μF is calculated, and the
next larger standard value of 4.7 μF is selected to limit noise on the BP5 regulator.
Input Voltage Filter Resistor (R11)
V
IN(min)
> 6.0 V so a 0 Ω resistor is placed in the VDD resistor location. If V
IN(min)
was < 6.0 V, an optional 1Ω to 2
Ω series VDD resistor could be used to filter switching noise from the device. Limit the voltage drop across this
resistor to less than 50 mV.
(24)
Driving the two FETs with 23 nC and 44 nC respectively, we calculate a maximum I
VDD
current of 43 mA and
would select a 1-Ωresistor.
Short Circuit Protection (R9)
The TPS40192/93 use the negative drop across the low-side FET during the OFF time to measure the inductor
current. The voltage drop across the low-side FET is given by Equation 25.
(25)
When 8 V ≤ V
IN
≤14 V, I
L(peak)
= 11.5 A Using the IRF7834 MOSFET, we calculate a peak voltage drop of
63.3 mV.
The TPS40192's internal temperature coefficient helps compensate for the MOSFET's R
DS(on)
temperature
coefficient. For this design select the short circuit protection voltage threshold of 110 mV by selecting R9 =
3.9 kΩ.
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