Datasheet

I
RMS(Cin)
+ I
IN(rms)
* I
IN(avg)
+
ǒ
I
OUT
)
1
12
I
RIPPLE
Ǔ
V
OUT
V
IN
Ǹ
*
V
OUT
I
OUT
V
IN
ESR
MAX
+
V
RIPPLE(esr)
I
LOAD
)
1
2
I
RIPPLE
C
IN(min)
+
I
LOAD
V
OUT
V
RIPPLE(cap)
V
IN
f
SW
I
L(peak)
+ I
OUT(max)
)
1
2
I
RIPPLE
) I
CHARGE
I
CHARGE
+
V
OUT
C
OUT
T
SS
ESR
MAX
t
V
RIPPLE(tot)
* V
RIPPLE(cap)
C
OUT
+
V
RIPPLE(tot)
*
ǒ
I
RIPPLE
C
OUT
f
SW
Ǔ
I
RIPPLE
TPS40192, TPS40193
www.ti.com SLUS719E –MARCH 2007–REVISED MAY 2013
(11)
Based on 178 μF of capacitance, 2.6-A ripple current, 600-kHz switching frequency and 36-mV ripple voltage,
calculate a capacitive ripple of 24.3 mV and a maximum ESR of 4.4 mΩ.
Two 1206 100-μF, 6.3-V X5R ceramic capacitors are selected to provide more than 178-μF of minimum
capacitance and less than 4.4 mΩ of ESR (2.5 mΩ each).
Peak Current Rating of the Inductor
With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum
saturation current rating for the inductor. The start-up charging current is approximated by Equation 12.
(12)
Using the TPS40192's minimum soft-start time of 3.0 ms, C
OUT
= 240 μF and V
OUT
= 1.8 V, I
CHARGE
= 144 mA.
(13)
Table 4. Inductor Requirements
PARAMETER SYMBOL VALUE UNITS
Inductance L 1.0 μH
RMS current (thermal rating) I
L(rms)
10.03
A
Peak current (saturation rating) I
L(peak)
11.3
A PG0083.102 1.0-μH is selected for its small size, low DCR (6.6 mΩ) and high current handling capability (12 A
thermal, 17 A saturation)
Input Capacitor Selection (C7)
The input voltage ripple is divided between capacitance and ESR. For this design V
RIPPLE(cap)
= 400 mV and
V
RIPPLE(ESR)
= 200 mV. The minimum capacitance and maximum ESR are estimated by Equation 14.
(14)
(15)
For this design C
IN
> 9.375 μF and ESR < 17.7 mΩ . The RMS current in the input capacitors is estimated by
Equation 16.
(16)
For this design V
IN
= 14 V, V
OUT
= 1.8 V, I
OUT
=10 A and I
RIPPLE
= 2.6 A calculate an RMS of 2.37 A, so the total
of our input capacitors must support 2.37 A of RMS ripple current.
Two 1210 10-μF 25V X5R ceramic capacitors with about 2 mΩ ESR and a 2-A
RMS
current rating are selected.
Higher voltage capacitors are selected to minimize capacitance loss at the DC bias voltage to ensure the
capacitors have sufficient capacitance at the working voltage.
MOSFET Switch Selection (Q1, Q2)
The switching losses for the high-side FET are estimated by Equation 17.
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