Datasheet

1
2
3
4
10
9
8
7
HDRV
SW
BOOT
LDRV
ENABLE
FB
COMP
VDD
U1
TPS40192DRC
5 6BP5PGD
GND
C6
470 nF
L1
1.0 µH
C8
2 × 100 µF
UDG-13106
R11
0 Ÿ
Q3
IRF7834
Q2
IRF7466
C7
2 × 10 µF
C11
1.0 µF
R12
100 NŸ
C5
4.7 µF
C4
1.0 µF
PGOOD
R4
100 NŸ
R6
4.22 NŸ
C3
10 nF
C1 100 pF
R9
3.9 NŸ
R8
20 NŸ
R10
2.61 NŸ
C2
1000 pF
R7
9.76 NŸ
R1
5.1 NŸ
R2
2 NŸ
Q1
2N7002W
V
IN
12 V
(8 V to 14 V)
V
IN
+
V
IN
±
Disable
V
OUT
1.0 V
10 A
V
OUT
+
V
OUT
±
Power
Ground
Signal
Ground
R14
100 NŸ
R13
0 Ÿ
TPS40192, TPS40193
www.ti.com SLUS719E –MARCH 2007–REVISED MAY 2013
DESIGN EXAMPLE
Introduction
This example illustrates the design process and component selection for a 12 V to 1.8 V point-of-load
synchronous buck regulator using the TPS40192. A definition of symbols used can be found in Table 8 of this
datasheet.
Table 3. Design Example Electrical Characteristics
PARAMETER TEST CONDITION MIN NOM MAX UNIT
V
IN
Input voltage 8 14
V
IN(ripple
Input ripple I
OUT
= 10 A 0.6 V
)
V
OUT
Output voltage 0 A ≤ I
OUT
≤ 10 A 1.764 1.800 1.836
Line regulation 8.0 V ≤ V
IN
≤ 14 V 0.5%
Load regulation 0 A ≤ I
OUT
≤ 10 A 0.5%
V
RIPPLE
Output ripple I
OUT
= 10 A 36
V
OVER
Output overshoot 3 A ≤ I
OUT
≤ 7 A 50 mV
V
UNDER
Output undershoot 50
I
OUT
Output current 0 10
A
I
SCP
Short circuit current trip point
η Efficiency V
IN
=12 V, I
OUT
= 5 A 90%
f
SW
Switching frequency 600 kHz
Size
The list of materials for this application is shown Table 7. The efficiency, line and load regulation from boards
built using this design are shown in Figure 17 and Table 3. Gerber Files and additional application information
are available from the factory.
Figure 17. TPS40192 Design Example Schematic
Design Example Considerations
• Optionally use R11 as a VDD filter resistor
• Locate the bypass capacitors (C7) near the power MOSFETs.
• Terminate signal components to a signal ground island separate from power ground
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: TPS40192 TPS40193