Datasheet

TPS40192, TPS40193

SLUS719E –MARCH 2007–REVISED MAY 2013

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Layout Recommendations and Sample Layout

Layout Recommendations:

• PowerPad™ is the only GND connection to the device (U1). PowerPad™ must be connected to ground.

• PowerPad™ should be directly connected to SYNC FET (Q3) source with short, wide trace.

• Locate 3-5 vias in PowerPad™ land to remove heat from the device.

• Connect input capacitors (C7 & C9) and output capacitors (C8 & C10) grounds directly to SYNC FET (Q3)

source with wide copper trace or solid power ground island.

• Locate input capacitors (C7 & C9), MOSFETs (Q2 & Q3), inductor (L1) and output capacitor (C8 & C10) over

power ground island.

• Use short, wide traces for LDRV and HDRV MOSFET connections.

• Route SW trace near HDRV trace.

• Route GND trace near LDRV trace.

• Use separate analog ground island under feedback components (C1, C2, C3, R5, R6, R7, R8 & R10).

• Connect ground islands at PowerPad™ with 10-mil wide trace opposite SYNC FET (Q2) source connection.

Sample Layout:

Figure 15. TPS40192/3 Sample Layout - Component Placement and Top Side Copper

Figure 16. TPS40192/3 Sample Layout - Bottom Side Copper (X-Ray view from Top)

Product Folder Links: TPS40192 TPS40193