Datasheet

TPS40192, TPS40193

www.ti.com

SLUS719E –MARCH 2007–REVISED MAY 2013

Pre-Bias Startup

The TPS40192/3 contains a unique circuit to prevent current from being pulled from the output during startup in

the condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level

(internal soft-start becomes greater than feedback voltage [V

]), the controller slowly activates synchronous

rectification by starting the first LDRV pulses with a narrow on-time. It then increments that on-time on a cycle-

by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This

scheme prevents the initial sinking of the pre-bias output, and ensures that the out voltage (V

OUT

) starts and

ramps up smoothly into regulation and the control loop is given time to transition from pre-biased startup to

normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of

switching until the low-side MOSFET is turned on for the full (1-D) interval is defined by 32 clock cycles.

Drivers

The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate-to-source voltage of 5 V.

The LDRV driver switches between VDD and GND, while HDRV driver is referenced to SW and switches

between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit to

minimize body diode conduction in the synchronous rectifier. The drivers are capable of driving MOSFETS that

are appropriate for a 15-A (TPS40192) or 20-A (TPS40193) converter.

Power Good

The TPS40192/3 provides an indication that output power is good for the converter. This is an open drain signal

and pulls low when any condition exists that would indicate that the output of the supply might be out of

regulation. These conditions include:

• V

is more than ±10% from nominal

• soft-start is active

• an undervoltage condition exists for the device

• a short circuit condition has been detected

• die temperature is over (145°C)

NOTE

When there is no power to the device, PGOOD is not able to pull close to GND if an

auxiliary supply is used for the power good indication. In this case, a built in resistor

connected from drain to gate on the PGOOD pull down device makes the PGOOD pin

look approximately like a diode to GND.

Thermal Shutdown

If the junction temperature of the device reaches the thermal shutdown limit of 145°C, the PWM and the oscillator

are turned off and HDRV and LDRV are driven low, turning off both FETs. When the junction cools to the

required level (125°C nominal), the PWM inititates soft start as during a normal power up cycle.

Product Folder Links: TPS40192 TPS40193