Datasheet

TPS40192, TPS40193
www.ti.com SLUS719E –MARCH 2007–REVISED MAY 2013
APPLICATION INFORMATION
Introduction
The TPS40192 and TPS40193 are cost optimized controllers providing all the necessary features to construct a
high performance DC/DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates
concerns about damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier N-
channel MOSFETs decrease switching losses for increased efficiency. Adaptive gate drive timing prevents shoot
through and minimizes body diode conduction in the rectifier MOSFET, also increasing efficiency. Selectable
short circuit protection thresholds and hiccup recovery from a short circuit increase design flexibility and minimize
power dissipation in the event of a prolonged output fault. The dedicated ENABLE pin allows the converter to be
placed in a very low quiescent current shutdown mode. Internally fixed switching frequency and soft-start time
reduce external component count, simplifying design and layout, as well as reducing footprint and cost. The 3
mm × 3 mm package size also contributes to a reduced overall converter footprint.
Voltage Reference
The band gap cell is designed with a trimmed 591-mV output. The 0.5% tolerance on the reference voltage
allows the user to design a very accurate power-supply.
Oscillator
The TPS40192 has a fixed internal switching frequency of 600 kHz. Tthe TPS40193 operates at a switching
frequency of 300 kHz.
UVLO
When the input voltage is below the UVLO threshold, the device holds all gate drive outputs in the low (OFF)
state. When the input rises above the UVLO threshold, and the ENABLE pin is above the turn ON threshold, the
oscillator begins to operate and the start-up sequence is allowed to begin. The UVLO level is internally fixed at
4.2 V.
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