Datasheet

UDG−05060
1.5 MΩ
1
2
3
9
8
SW
BOOT
ENABLE
FB
COMP
TPS40190
4
5
6
BP5
VDD
GND
7
LDRV
5−V
Regulator
VDD
Oscillator
Fault
Controller
PWM Logic
and
Anti−Cross
Conduction
Short Circuit
Threshold
Selector
+
SC OC
CLK
10 HDRV
Soft−Start
Ramp
Generator
FAULT
SD
UVLO
SC
Threshold Latch
SS
5 V
5 V
+
+
4.25 V
UVLO
5 V
+
+
SS
591 mV
Error Amplifier
PWM
Comparator
CLK
SC Threshold Latch
SC: 160 mV, 320 mV
or 460 mV below VDD
UVLO
FAULT
TPS40190
SLUS658C –JULY 2005–REVISED JULY 2012 www.ti.com
APPLICATION INFORMATION
Introduction
The TPS40190 is a cost optimized controller providing all the necessary features to construct a high-performance
DC-DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates concerns about
damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier N-channel MOSFETs
decrease switching losses for increased efficiency. Adaptive gate drive timing minimizes body diode conduction
in the rectifier MOSFET, also increasing efficiency. Selectable short circuit protection thresholds and hiccup
recovery from a short-circuit increase design flexibility and minimize power dissipation in the event of a prolonged
output fault. A dedicated enable pin (ENABLE) allows the converter to be placed in a very low quiescent current
shutdown mode.
Internally fixed switching frequency and soft-start time reduce external component count, simplifying design and
layout, as well as reducing footprint and cost. The 3 mm × 3 mm package size also contributes to a reduced
overall converter footprint.
Internally Fixed Parameters
The TPS40190 has a fixed internal switching frequency of 300 kHz. Soft-start time is fixed at 4.7 ms typical and
the UVLO level is set between 4.1 V and 4.4 V.
6 Copyright © 2005–2012, Texas Instruments Incorporated