Datasheet

DRC PACKAGE

(TOP VIEW)

GND

VDD

COMP

ENABLE

6 7 8 9 10

BP5 LDRV BOOT SW HDRV

TPS40190DRC

TPS40190

www.ti.com

SLUS658C –JULY 2005–REVISED JULY 2012

DEVICE INFORMATION

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME NO.

BOOT 8 I Power supply for the flying high-side driver

Output bypass for the internal regulator. Connect 4.7-μF capacitor from this pin to GND. Low power, low

BP5 6 O noise loads may be connected here if desired. The sum of the external load and the gate drive requirements

must not exceed 40 mA. The regulator is turned off when the ENABLE pin is pulled low.

Output of the error amplifier. Connecting a resistance from COMP to GND sets the output short circuit

COMP 3 O

detection threshold. See applications information for details.

Logic level input that starts or stops the controller from an external user command. A high level turns the

controller on. This pin has a high-impedance internal pull-up integrated into the device. Because this pin is

ENABLE 1 I

high impedance, a 10-nF capacitor to ground or an external pull-up resistor (100 kΩ) to VDD is

recommended to avoid noise coupling to this pin.

FB 2 I Inverting input to the error amplifier

GND 5 - Common connection for the controller

HDRV 10 O Bootstrapped output for driving the gate of the high side N channel FET.

LDRV 7 O Output to the rectifier FET gate

Sense line for the adaptive anti cross conduction circuitry. Serves as common connection for the flying high

SW 9 I

side FET driver

VDD 4 I Power input to the controller