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5.3 Start Up and Test Procedure
5.4 Control Loop Gain and Phase Measurement Procedure
7. The control loop gain can be measured by
20 LOG
ǒ
ChannelB
ChannelA
Ǔ
.
5.5 Stackable EVM Configuration
5.5.1 Single Phase Operation (Default)
5.5.2 Multi-Phase Operation
Test Set Up
1. Ensure LOAD is set to constant current mode and to sink 0A DC.
2. Increase V
IN
from 0V to 12V, V
OUT
should be in regulation per Table 1 .
3. Vary LOAD from 0–20Adc, V
OUT
should remain in regulation per Table 1 for all combinations of load on
LOAD up to 20A.
4. Vary V
IN
from 10.8V to 13.2V, V
OUT
should remain in regulation per Table 1 for all combinations of load
on LOAD up to 20A.
1. Connect 1 kHz–1MHz isolation transformer to test points marked TP9 and TP10.
2. Connect input signal amplitude measurement probe (channel A) to TP9.
3. Connect output signal amplitude measurement probe (channel B) to TP10.
4. Connect ground lead of channel A and channel B to TP13.
5. Inject 25mV or less signal through the isolation transformer.
6. Sweep the frequency from 100Hz to 1MHz with 10Hz or lower post filter.
8. Control loop phase is measured by the phase difference between Channel A and Channel B.
9. Disconnect isolation transformer from the bode plot test points before making other measurements
(Signal Injection into Feedback may interfere with accuracy of other measurements).
JP1 and JP2 are used to set master and slave configuration. J4 is used to configure the clock scheme. In
default, for a single phase operation, JP1, JP2 are left open to configure the IC as a master. To configure
as a slave insert jumpers on JP1 and JP2. J4 is also left open to generate an 8 phase CLKIO for
interleaving with 45 degree separation. If a 6 phase CLKIO is desired, then short J4 to R23 which is
29.4k Ω .
Table 2. Master Clock Scheme Selection
J4 (PSEL Resistance to GND) Mode
0 No CLKIO Single phase operation
open 8 phase CLKIO Multi phase operation 2, 4, 8, 12, 16
29.4k Ω (R23) 6 phase CLKIO Multi phase operation 2, 3, 6, 9, 12,15
Here, a two phase operation is given as an example. Two identical TPS40180 EVM boards are stacked
together to construct a two phase converter as shown in Figure 5 . The boards are connected with J5 or
J6. J5 and J6 are basically the same however located on the different side of the board. Select one EVM
as the master board and configure it as shown in 5.5.1. Then use jumpers to short JP1 and JP2 to
configure the other board as a slave. J4 on the slave board will determine the slave IC synchronization
phase angle. Short J4 at the appropriate position to get the desired phase angle. Table 3 and Table 4
show the relationship between phase angle and PSEL resistance.
8 Using the TPS40180EVM, A 20A Stackable Single Phase Synchronous Buck Converter SLVU213 – May 2007
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