Datasheet

UDG-09218
1 19 20
8-V
Regulator
3.3-V
Regulator
Input and
Regulators OK
ENABLE VIN UVLO
10VDD
4RT
2SYNC
3M/S
Oscillator
and
Synchronization
Run
+
PWM Logic
Anti-Cross
Conduction
Run
Fault
V
IN
+
+
+
TRK
Error
Amplifier
6
SS
EAMP
V
REF
FB
7
Run
COMP 8
AGND 9
Over-Temperature
Fault Controller
T
J
CLK
Overcurrent
Fault Controller
V
IN
Run
SW
LDRV
CLK
12ILIM
Run
OC_FAULT
Soft-Start
and
Fault Logic
T_FAULT
Power Good
Controller
V
REF
FB
18 BOOT
17
HDRV
16 SW
15 VBP
14 LDRV
13 PGND
Gate Drivers
V
BP
Run
Run
11 PGOOD
5 SS
SS
EAMP
CLK
RAMP
TPS40170
VBP
PWM
Comparator
FAULT
FAULT
Reset
Run
Run
TPS40170
SLUS970A –MARCH 2011–REVISED NOVEMBER 2013 www.ti.com
PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NAME NO.
8-V regulated output for gate driver. A ceramic capacitor with a value between 1 µF and 10 µF must be
VBP 15 O
connected from this pin to PGND
3.3-V regulated output. A ceramic by-pass capacitor with a value between 0.1 µF and 1 µF must be
VDD 10 O
connected between this pin and the AGND pin and placed closely to this pin.
Input voltage for the controller which is also the input voltage for the DC/DC converter. A 1-µF by-pass
VIN 19 I
capacitor from this pin to AGND must be added and placed closed to VIN.
DEVICE BLOCK DIAGRAM
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