Datasheet

19
18
17
16
15
14
13
12
1 20
2
3
4
5
6
7
8
10
9
11
SW
BOOT
LDRV
PGND
HDRV
VIN
UVLO
PGOOD
VBP
ILIM
TRK
SS
FB
RT
M/S
COMP
AGND
SYNC
VDD
ENABLE
TPS40170
TPS40170
www.ti.com SLUS970A –MARCH 2011–REVISED NOVEMBER 2013
DEVICE INFORMATION
RGY PACKAGE
QFN-20
(Top View)
PIN FUNCTIONS
PIN
I/O DESCRIPTION
NAME NO.
AGND 9 — Analog signal ground. This pin must be electrically connected to power ground PGND externally.
BOOT 18 O Boot capacitor node for high-side FET gate driver. The boot capacitor is connected from this pin to SW.
Output of the internal error amplifier. The feedback loop compensation network is connected from this pin
COMP 8 O
to the FB pin.
This pin must be high for the device to be enabled. If this pin is pulled low, the device is put in a low-power
ENABLE 1 I
consumption shutdown mode.
Negative input to the error amplifier. The output voltage is fed back to this pin through a resistor divider
FB 7 I
network.
HDRV 17 O Gate driver output for the high-side FET.
A resistor from this pin to PGND sets the overcurrent limit. This pin provides source current used for
ILIM 12 I
overcurrent protection threshold setting.
Gate driver output for the low-side FET. Also, a resistor from this pin to PGND sets the multiplier factor to
LDRV 14 O determine short-circuit current limit. If no resistor is present the multiplier defaults to 7 times the ILIM pin
voltage.
Master or slave mode selector pin for frequency synchronization. This pin must be tied to VIN for master
M/S 3 I mode. In the slave mode this pin must be tied to AGND or left floating. If the pin is tied to AGND, the device
synchronizes with a 180° phase shift. If the pin is left floating, the device synchronizes with a 0° phase shift.
PGND 13 — Power ground. This pin must externally connect to the AGND at a single point.
Power good indicator. This pin is an open-drain output pin and a 10-kΩ pull-up resistor is recommended to
PGOOD 11 O
be connected between this pin and VDD.
A resistor from this pin to AGND sets the oscillator frequency. Even if operating in slave mode, it is required
RT 4 I
to have a resistor at this pin to set the free running switching frequency.
SS 5 I Soft-start. A capacitor must be connected at this pin to AGND. The capacitor value sets the soft-start time.
This pin must connect to the switching node of the synchronous buck converter. The high-side and low-side
SW 16 I
FET current sensing are also done from this node.
Synchronization. This is a bi-directional pin used for frequency synchronization. In the master mode, it is
SYNC 2 I/O
the SYNC output pin. In the slave mode, it is a SYNC input pin. If unused, this pin can be left open.
Tracking. External signal at this pin is used for output voltage tracking. This pin goes directly to the internal
TRK 6 I error amplifier as a positive reference. The lesser of the voltages between V
TRK
and the internal 600-mV
reference sets the output voltage. If not used, this pin should be pulled up to VDD.
Undervoltage lockout. A resistor divider on this pin from VIN to AGND can be used to set the UVLO
UVLO 20 I
threshold.
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