Datasheet

TPS40170
www.ti.com SLUS970A –MARCH 2011–REVISED NOVEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for -40ºC ≤ T
J
≤ 125ºC, V
VIN
=12 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ERROR AMPLIFIER
GBWP
(2)
Gain bandwidth product 7 10 13 MHz
A
OL
(2)
Open-loop gain 80 90 95 dB
I
IB
Input bias current 100 nA
I
EAOP
Output source current V
VFB
= 0 V 2 mA
I
EAOM
Output sink current V
VFB
= 1 V 2 mA
PROGRAMMABLE SOFT START
I
SS(source,start)
Soft-start source current at V
SS
< 0.5 V V
SS
= 0.25 V 42 52 62 µA
I
SS(source,normal)
Soft-start source current at V
SS
> 0.5 V V
SS
= 1.5 V 9.3 11.6 13.9 µA
I
SS(sink)
Soft-start sink current V
SS
= 1.5 V 0.77 1.05 1.33 µA
SS pin HIGH voltage during fault (OC or
V
SS(fltH)
2.38 2.50 2.61 V
thermal) reset timing
SS pin LOW voltage during fault (OC or
V
SS(fltL)
235 300 375 mV
thermal) reset timing
V
SS(steady_state)
SS pin voltage during steady-state 3.25 3.30 3.50 V
Initial offset voltage from SS pin to error
V
SS(offst)
525 650 775 mV
amplifier input
TRACKING
V
TRK(ctrl)
(2)
Range of TRK which overrides V
REF
4.5 V < V
IN
≤ 60 V 0 600 mV
SYNCHRONIZATION (MASTER/SLAVE)
V
MSTR
M/S pin voltage in master mode 3.9 VIN V
V
SLV(0)
M/S pin voltage in slave 0 deg mode 1.25 1.75 V
V
SLV(180)
M/S pin voltage in slave 180 deg mode 0 0.75 V
I
SYNC(in)
SYNC pin pull-down current 8 11 14 µA
V
SYNC(in_high)
SYNC pin input high-voltage level 2 V
M/S configured as slave- 0 degrees or
V
SYNC(in_low)
SYNC pin input low-voltage level 0.8 V
slave-180 degrees
t
SYNC(high_min)
Minimum SYNC high pulse-width 40 50 ns
t
SYNC(low_min)
Minimum SYNC low pulse-width 40 50 ns
GATE DRIVERS
R
HDHI
High-side driver pull-up resistance 1.37 2.64 3.50 Ω
R
HDLO
High-side driver pull-down resistance 1.08 2.40 3.35 Ω
C
LOAD
= 2.2 nF, I
DRV
= 300 mA
R
LDHI
Low-side driver pull-up resistance 1.37 2.40 3.20 Ω
R
LDLO
Low-side driver pull-down resistance 0.44 1.10 1.70 Ω
t
NON-OVERLAP1
Time delay between HDRV fall and LDRV rise 50
C
LOAD
= 2.2 nF,
ns
V
HDRV
= 2 V, V
LDRV
= 2 V
t
NON-OVERLAP2
Time delay between HDRV rise and LDRV fall 60
OVERCURRENT PROTECTION (LOW-SIDE MOSFET SENSING)
I
ILIM
ILIM pin source current 9.00 9.75 10.45
4.5 V < V
IN
< 60 V, T
J
= 25°C µA
I
ILIM,(ss)
ILIM pin source current during Soft-start 15
I
ILIM, Tc
(2)
Temperature coefficient of ILIM current 4.5 V < V
IN
< 60 V 1400 ppm
V
ILIM
(2)
ILIM pin voltage operating range 4.5 V < V
IN
< 60 V 50 300 mV
Overcurrent protection threshold (Voltage R
ILIM
= 10 kΩ, I
ILIM
= 10 µA
OCP
TH
–110 –100 –84 mV
across low-side FET for detecting overcurrent) (V
ILIM
= 100 mV)
SHORT CIRCUIT PROTECTION HIGH-SIDE MOSFET SENSING)
V
LDRV(max)
LDRV pin maximum voltage during calibration R
LDRV
= open 300 360 mV
A
OC3
R
LDRV
= 10 kΩ 2.75 3.20 3.60 V/V
Multiplier factor to set the SCP based on OCP
A
OC7
R
LDRV
= open 6.40 7.25 7.91 V/V
level setting at the ILIM pin
A
OC15
R
LDRV
= 20 kΩ 13.9 16.4 18.0 V/V
(2) Specified by design. Not production tested.
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