Datasheet

TPS40170
SLUS970A –MARCH 2011–REVISED NOVEMBER 2013 www.ti.com
Layout Recommendations
Figure 39 illustrates an example layout. For the controller, it is important to carefully connect noise sensitive
signals such as RT, SS, FB, and comp as close to the IC as possible and connect to AGND as shown. The
PowerPad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The
AGND and PGND should be connected at a single point.
When using high-performance FETs such as NexFET™ from Texas Instruments, careful attention to the layout is
required. Minimize the distance between positive node of the input ceramic capacitor and the drain pin of the
control (high-side) FET. Minimize the distance between the negative node of the input ceramic capacitor and the
source pin of the syncronization (low-side) FET. Becasue of the large gate drive, smaller gate charge, and faster
turn-on times of the high-performance FETs, it is recommended to use a minimum of 4, 10 -µF ceramic input
capacitors such as TDK #C3216X5R1A106M. Ensure the layout allows a continuous flow of the power planes.
The layout of the HPA578 EVM is shown in Figure 39 through Figure 42 for reference.
Figure 39. Top Copper, Viewed From Top
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