Datasheet

( )
= = =
G1
BOOST
BOOT ripple
Q
25nC
C 100nF
V 250mV
( ) ( )
( )
( )
> = W = W » W
-
-
UVLO(max)
UVLO set UVLO hys
UVLO _ ON(min) UVLO(max)
V
0.919 V
R R 200k 22.7k 22.1k
9.0 V 0.919 V
V V
( )
( ) ( )
-
-
= = = W
m
UVLO on UVLO off
UVLO hys
UVLO
V V
9 V 8 V
R 200k
I 5.0 A
( ) ( )
= - W = - = W » W
4 4
RT
SW
10 10
R 2k 2 31.3k 31.6k
f 300kHz
( )
-
æ ö
´
= + ´ ´
ç ÷
è ø
9
FD OUT G
DRIVE SW
DRIVE SW
V I Q
W
J 10 V f
nC
I Q
( )
( )
( )
( )
( )
-
-
æ ö
= + ´ ´ -
ç ÷
W
è ø
2
3 2
OUT
1
OUT P P
12
IN
V
W
K 10 I I 1
m
V
( )
( )
( )
( )
( )
-
-
æ ö
= + ´ ´
ç ÷
W
è ø
2
3 2
OUT
1
OUT P P
12
IN
V
W
K 10 I I
m
V
( )
( )
-
æ ö
´
= ´ + ´ ´
ç ÷
è ø
9
IN OUT G
DRIVE SW
DRIVE SW
V I Q
W
J 10 V f
nC
I Q
TPS40170
www.ti.com SLUS970A –MARCH 2011–REVISED NOVEMBER 2013
MOSFET Switch Selection (Q1, Q2)
Using the J/K method for MOSFET optimization, apply Equation 30 through Equation 33.
High-side gate (Q1):
(30)
(31)
Low-side gate (Q2):
(32)
(33)
Optimizing for 300 kHz, 24-V input, 5-V output at 6 A, calculate ratios of 5.9 mΩ/nC and 0.5 mΩ/nC for the high-
side and low-side FETS respectively. BSC110N06NS2 (Ratio 1.2) and BSC076N06NS3 (Ratio 0.69) MOSFETS
are selected.
Timing Resistor (R7)
The switching frequency is programmed by the current through R
RT
to GND. The R
RT
value is calculated using
Equation 34.
(34)
UVLO Programming Resistors (R2, R6)
The UVLO hysteresis level is programmed by R2 using Equation 35.
(35)
(36)
Boot-Strap Capacitor (C7)
To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than
250 mV.
(37)
VIN Bypass Capacitor (C18)
Place a capacitor with a a value of 1.0 µF. Select a capacitor with a value between 0.1 µF and 1.0 µF, X5R or
better ceramic bypass capacitor for VIN as specified in RECOMMENDED OPERATING CONDITIONS . For this
design a 1.0-µF, 100 V, X7R capacitor has been selected.
VBP Bypass Capacitor (C19)
Select a capacitor with a value between 1.0 µF and 10 µF, X5R or better ceramic bypass capacitor for BP as
specified in RECOMMENDED OPERATING CONDITIONS. For this design a 4.7-µF, 16 V capacitor has been
selected.
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