Datasheet
TPS40170
www.ti.com
SLUS970A –MARCH 2011–REVISED NOVEMBER 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN MAX UNIT
VIN –0.3 62
M/S –0.3 VIN
UVLO –0.3 16
Input voltage V
SW –5 V
VIN
SW (for duration less than 200 ns), -10 V
VIN
BOOT V
SW
+ 8.8
HDRV V
SW
BOOT
BOOT-SW, HDRV-SW (differential from BOOT or –0.3 8.8
HDRV to SW)
Output voltage V
VBP, LDRV, COMP, RT, ENABLE, PGOOD, SYNC –0.3 8.8
VDD, FB, TRK, SS, ILIM –0.3 3.6
AGND-PGND, PGND-AGND 200 200
mV
PowerPAD to AGND (must be electrically connected 0
external to device)
Human body model (HBM) 2
Electrostatic discharge (ESD) kV
Charge device model (CDM) 1
Lead Temperature 260 °C
Operating junction temperature range T
J
–40 125 °C
Storage temperature T
stg
–55 150 °C
THERMAL INFORMATION
TPS40170
THERMAL METRIC
(1)
RGY UNITS
20 PINS
θ
JA
Junction-to-ambient thermal resistance
(2)
35.0
θ
JC(top)
Junction-to-case(top) thermal resistance
(3)
36.7
θ
JB
Junction-to-board thermal resistance
(4)
12.6
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
0.4
ψ
JB
Junction-to-board characterization parameter
(6)
12.7
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
3.1
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
IN
Input voltage 4.5 60 V
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links :TPS40170