Datasheet

( )

= - -

BP DFWD PRE BIAS

GATE hs

V V V V

TPS40170

SLUS970A –MARCH 2011–REVISED NOVEMBER 2013

www.ti.com

NOTE

When output is pre-biased at V

PREBIAS

, that voltage also applies to the SW node during

start-up. When the pre-bias circuitry commands the first few high-side pulses before the

first low-side pulse is initiated, the gate voltage for the high-side MOSFET is as described

in Equation 18. Alternatively, If pre-bias level is high, it is possible that SCP can be tripped

due to high turn-on resistance of the high-side MOSFET with low gate voltage. Once

tripped, the device resets and then attempts to re-start. The device may not be able to

start up until output is discharged to a lower voltage level by either an active load or

through feedback resistors.

In the case of a a high pre-bias level, a low gate-threshold voltage rated device is

recommended for the high-side MOSFET and increasing the SCP level also helps

alleviate the problem.

where

• V

GATE(hs)

is the gate voltage for the high-side MOSFET

• V

is the BP regulator output

• V

DFWD

is bootstrap diode forward voltage (18)

Product Folder Links :TPS40170