Datasheet

TPS40170

www.ti.com

SLUS970A –MARCH 2011–REVISED NOVEMBER 2013

Adaptive Drivers

The drivers for the external high-side and low-side MOSFETs are capable of driving a gate-to-source voltage,

VBP

. The LDRV driver for the low-side MOSFET switches between VBP and PGND, while the HDRV driver for

the high-side MOSFET is referenced to SW and switches between BOOT and SW. The drivers have non-

overlapping timing that is governed by an adaptive delay circuit to minimize body diode conduction in the

synchronous rectifier.

Start-Up Into Pre-Biased Output

The TPS40170 contains a circuit to prevent current from being pulled out of the output during startup in case the

output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start

becomes greater than feedback voltage [V

VFB

]), the controller slowly activates synchronous rectification by

starting the first LDRV pulses with a narrow on-time (see Figure 33), where:

• V

= 5 V

• V

OUT

= 3.3 V

• V

PRE

= 1.4 V

• f

= 300 kHz

• L = 0.6 µH

It then increments the on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D

is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensures

that the output voltage (V

OUT

) starts and ramps up smoothly into regulation and the control loop is given time to

transition from pre-biased startup to normal mode operation with minimal disturbance to the output voltage. The

time from the start of switching until the low-side MOSFET is turned on for the full (1-D) interval is between

approximately 20 and 40 clock cycles.

Figure 33. Start-Up Switching Waveform During Pre-Biased Condition

If the output is pre-biased to a voltage higher than the voltage commanded by the reference, then the PWM

switching does not start.

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