Datasheet

V
HDRV
V
SYNC
Synchronized duration 20-ms transition duration Free running duration .
f
S
= SYNC clock frequency f
S
= 0.7 x running frequency f
S
= free running frequency
SYNC clock pulse missing
UDG-09207
TPS40170
SLUS970A –MARCH 2011–REVISED NOVEMBER 2013 www.ti.com
TPS40170 provides a smooth transition for the SYNC clock signal loss at slave mode. In slave mode, a
synchronization clock signal is provided externally through the SYNC pin to the device. The switching frequency
is synchronized to the external SYNC clock signal. If for some reason the external clock signal is missing, the
device switching frequency is automatically overridden by a transition frequency which is 0.7 times its
programmed free running frequency. This transition time is approximately 20 μs. After that, the device switching
frequency is changed to its programmed free running frequency. Figure 25 shows this process.
Figure 25. Transition for SYNC Clock Signal Missing (for Slave-180 Mode)
NOTE
When the device is operating in the master mode with duty ratio around 50%, PWM
jittering may occur. Always configure the device into the slave mode by either connecting
the M/S pin to GND or leaving it floating if master mode is not used.
When external SYNC clock signal is used for synchronization, limit maximum slew rate of
the clock signal to 10 V/µs to avoid potential PWM jittering and connect the SYNC pin to
the external clock signal via a 5 kΩ resistor.
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