Datasheet

OUT
RIPPLE
sw
V
I = × 0.455 = 1.573A
L × f
L
N
PH
TPS40140
SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013 www.ti.com
6.3 Example 3: Four-Phase Single Output Configuration From 12 V to 1.8 V DC-to-DC
Converter Using Two TPS40140
The following example illustrates the design process and component selection for a four phase single
output synchronous buck converter using two TPS40140.
Here, two modules are designed. One is a master module. The other one is a slave module. Each module
contains two phases and each phase handle 5-A. The two modules are stacked together to form a 4-
phase converter. More slave modules can be stacked to this converter to get the desired phases. The
modules are plugged into a mother board.
The design goal parameters are given in Table 6-3.
Table 6-3. Design Goal Parameters
PARAMETER TEST CONDITION MIN TYP MAX UNIT
V
IN
Input Voltage 10.8 12 13.2 V
V
OUT
Output voltage 1.8 V
V
RIPPLE
Output ripple I
O
= 20 A 1%V
O
V
I
PH
Phase current 5 A
f
sw
Switching frequency 650 kHz
N
PH
Phase number 4
6.3.1 Step 1: Output Capacitor Selection
The output capacitor is typically selected by the output load transient response requirement. Equation 23
in the dual output design example is used. Also, as mentioned in the two phase design example, the
inductor is equivalent to . Based on a 10A load transient with a maximum of 30 mV deviation, a
minimum 370μF output capacitor is required. In the design, one 180μF, 6.3V, SP capacitor is placed on
the mother board. Four 22-μF, 6,3V ceramic capacitors are placed on each module. The total output
capacitance is 356 μF.
The output ripple current cancellation factor is calculated to be 0.455 based on Equation 57.
So the maximum output ripple current is calculated by:
(61)
With 356μF output capacitance, the ripple voltage at the capacitor is calculated to be 850 μV. In the
specification, the output ripple voltage should be less than 18 mV, so based on Equation 24, the required
maximum ESR is 11 mΩ. The selected capacitors can reach this requirement.
6.3.2 Step 2: Input Capacitor Selection
The input voltage ripple depends on the input capacitance and the ESR. The minimum capacitor and the
maximum ESR can be estimated by Equation 25 and Equation 26 in the dual output design example.
For this design, assume is 50mV and is 30mV, also each phase inductor ripple current is 50%, so the
calculated minimum capacitance is 93-μF and the maximum ESR is 4.6 mΩ. In this case, one 33-μF 6.3-V
SP-capacitor is placed on the mother board and each module has two 22-μF, 6.3-V ceramic capacitors.
The maximum input ripple RMS current is calculated to be 2.57 A with the minimum input voltage based
on Equation 59. The selected capacitors are sufficient to meet this requirement.
54 DESIGN EXAMPLES Copyright © 2005–2013, Texas Instruments Incorporated
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