Datasheet

I
RIPPLE
+
V
OUT
L f
SW
DI
OUT
ǒ
N
PH
, D
Ǔ
+ 4.374 A
Õ
Õ
PH
PH
N
PH
i=1
OUT PH
N -1
PH
i=1
i - N × D
ΔI (N , D) =
( i - N × D +1)
TPS40140
SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013 www.ti.com
6.2 Example 2: Two-Phase Single Output Configuration From 12 V to 1.5 V DC/DC
Converter Using a TPS40140
The following example illustrates the design process and component selection for a two-phase single
output synchronous buck converter using TPS40140. The design goal parameters are given in Table 6-2.
The inductor and MOSFET selection equations are quite similar to the dual output converter design, so
they are not repeated here.
Table 6-2. Design Goal Parameters
PARAMETER TEST CONDITION MIN TYP MAX UNIT
V
IN
Input Voltage 10.8 12 13.2 V
V
OUT
Output voltage 1.5 V
V
RIPPLE
Output ripple I
O
= 32A 2%Vo V
I
OUT1
Output current 32 A
f
sw
Switching frequency 500 kHz
6.2.1 Step 1: Output Capacitor Selection
The output capacitor is typically selected by the output load transient response requirement. Equation 23
in the dual output design example is used. The inductor L in the equation is equal to the phase inductance
divided by number of phases.
Based on a 15-A load transient with a maximum of 30 mV deviation, a minimum 1.32-μF output capacitor
is required. In the design, four 330-μF, 2 V, SP capacitor are selected to meet this requirement. Each
capacitor has an ESR of 6 mΩ.
Another criterion for capacitor selection is the output ripple voltage that is determined mainly by the
capacitance and the ESR.
Due to the interleaving of channels, the total output ripple current is smaller than the ripple current from a
single phase. The ripple cancellation factor is expressed in Equation 57.
(57)
where
• D is the duty cycle for a single phase
• N
PH
is the number of active phases, here it is equal to 2
The maximum output ripple current is then calculated in Equation 58.
(58)
With 1.32 mF output capacitance, the ripple voltage at the capacitor is calculated to be 828 μV. In the
specification, the output ripple voltage should be less than 30 mV, so based on Equation 24, the required
maximum ESR is 6.7 mΩ. The selected capacitors can meet this requirement.
6.2.2 Step 2: Input Capacitor Selection
The input voltage ripple depends on the input capacitance and the ESR. The minimum capacitor and the
maximum ESR can be estimated by Equation 25 and Equation 26 in the dual output design example.
For this design, V
RIPPLE(CIN)
assume is 100mV and V
RIPPLE(CinESR)
is 50 mV, also the inductor ripple current
I
RIPPLE
is 30%, so the calculated minimum capacitance is 40 μF and the maximum ESR is 2.7 mΩ.
Choosing four 22-μF, 16-V, 2-mΩ ESR ceramic capacitors meet this requirement.
50 DESIGN EXAMPLES Copyright © 2005–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS40140