Datasheet

ESR
OUT
1
f = = 176.8kHz
2 × π × C × ESR
VCP1
OUT OUT
1
f = = 2.36kHz
2 × π × C × R
S
OUT
RAMP
IN OUT OUT
RAMP
t
t
V
V
DCR Ac
t L
ln
V V 2 V
V
DCR Ac DCR Ac
t L L
=
æ ö
æ ö
æ ö
æ ö
- ´ ´
ç ÷
ç ÷
ç ÷
ç ÷
è ø
è ø
ç ÷
è ø
ç ÷
- ´
æ ö
æ ö
ç ÷
- ´ ´ - ´ ´
ç ÷
ç ÷
ç ÷
è ø
è ø
è ø
OUT OUT
s OUT OUT
(s × C × ESR +1)× R
1 1
Gvc(s) = × ×
DCR × Ac s × τ + 1 s × C ×R +1
( )
3 9 3
SS SS
t C 58 10 22 10 58 10 1.28ms
-
= ´ ´ = ´ ´ ´ =
boot
Qg 8nc
C = = = 16nF
ΔV 0.5V
TPS40140
www.ti.com SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013
6.1.5.12 BOOT1 and SW1 (pin 27 and 25)
A bootstrap capacitor is connected between the BOOT1 and SW1 pin. The bootstrap capacitor depends
on the total gate charge of the high side MOSFET and the amount of droop allowed on the bootstrap
capacitor.
(45)
For this application, a 0.1-μF capacitor is selected.
6.1.5.13 TRK1 (pin 33)
A 22-nF capacitor is tied to TRK1 pin to provide 1.28-ms of soft-start time.
(46)
6.1.5.14 DIFFO, VOUT and GSNS (pin 1, pin 2 and pin 3)
VOUT and GSNS are connected to the remote sensing output connector. DIFFO is connected to the
feedback resistor divider. If the differential amplifier is not used, VOUT and GSNS are suggested to be
grounded, and DIFFO is left open.
6.1.6 Feedback Compensator Design (COMP1 pin 35)
Peak current mode control method is employed in the controller. A small signal model is developed from
the COMP signal to the output.
(47)
The time constant is defined by:
(48)
The low frequency pole is calculated by:
(49)
The ESR zero is calculated by:
(50)
In this design, a Type II compensator is employed to compensate the loop.
Copyright © 2005–2013, Texas Instruments Incorporated DESIGN EXAMPLES 47
Submit Documentation Feedback
Product Folder Links: TPS40140