Datasheet

TPS40140
www.ti.com SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013
2 DEVICE RATINGS
2.1 ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD, UVLO ≤ VDD, RT, SS –0.3 16
SW1, SW2 –1 44
Input voltage range
SW1, SW2, transient < 50 ns –5 V
BOOT1, BOOT2, HDRV1, HDRV2 V
SW
+ 6.0
All other pins –0.3 6.0
Output current RT 200 μA
Human body model 3000
Electrostatic dischage V
Charged device model 1500
Operating junction temperature, T
J
–40 150 °C
Storage junction temperature, T
J
–55 150 °C
2.2 RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
VDD, UVLO ≤ VDD –0.3 15
SW1, SW2 –1 40
Input voltage V
BOOT1, BOOT2, HDRV1, HDRV2 V
S W
+5.5
All other pins –0.3 5.5
Maximum output current RT 25 μA
Operating free-air –40 85 °C
temperature
2.3 THERMAL INFORMATION
TPS40140
THERMAL METRIC RHH UNITS
36 PINS
θ
JA
Junction-to-ambient thermal resistance
(1)
30.8
θ
JCtop
Junction-to-case (top) thermal resistance
(2)
18.4
θ
JB
Junction-to-board thermal resistance
(3)
5.9
°C/W
ψ
JT
Junction-to-top characterization parameter
(4)
0.2
ψ
JB
Junction-to-board characterization parameter
(5)
5.9
θ
JCbot
Junction-to-case (bottom) thermal resistance
(6)
0.7
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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