Datasheet

SET

+ V

OUT

IN2

IN1

100 kW

TPS40140

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SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013

in the 6th or 8th position. With the missing pulse, the phase synchronization of the master, to the missing

pulse, can be controlled by the voltage on the PHSEL pin. See the section on DIGITAL CLOCK

SYNCHRONIZATION. Phase shifting would also be desirable if more than one controller were to be

synchronized to the same external clock. The high-level threshold for the external clock is 3.2 V, and the

low-level threshold is 0.5 V. The typical duty ratio is approximately 0.5.

Figure 5-7 shows a time slice of the two external clock possibilities and the resulting PWM signal. EXT

CLK-A is the continuous clock with no missing pulse and the PWM-A signal could be frequency

synchronized anywhere in the clock stream. The PWM signal is at 1/8 of the EXT CLK-A frequency. EXT

CLK-S is the external clock stream with a missing pulse every 8 cycles. The phasing of the PWM-S is

based on the voltage on the PHSEL pin. For PHSEL grounded, the PWM-S signal is shifted 90 degrees

from what would be the falling edge of the missing pulse as shown in Figure 5-7.

If the controller has free running operation (in clock master mode) before receiving the external clock, the

switching frequency is set by connecting a resistor from the RT pin to GND. In order to receive the

external clock, the PHSEL pin should be connected to GND to disable the output of CLKIO pin. A 500-Ω

resistor is recommended to be placed between the external clock and the CLKIO pin. When dynamically

shorting the RT pin to BP5 through a switch, the controller switches to clock slave mode and starts to

synchronize to the external clock.

5.22 SPLIT INPUT VOLTAGE OPERATION

It may be advantageous to operate a master controller’s power stages from V

IN 1

, different from the slave

controller(s) power stages, V

IN 2

where V

IN 1

> V

IN 2

. This enables the system designer to optimize the

current taken from the system input voltages. In order to balance the output currents, a programmed offset

is applied to ILIM2 of the slave controller(s). The voltage on this pin sets the offset current for channel 2.

The ramp offset is determined by a resistor, R

SET

, connected to the ILIM2 pin of the slave, and is given by:

(7)

5.23 CURRENT SENSE

The current sensing and overcurrent detection architecture is shown in Figure 5-8.

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