Datasheet

TPS40140
SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013 www.ti.com
5.11 POWER ON RESET (POR)
The internal POR function ensures the VREG and BP5 voltages are within their regulation windows before
the controller is allowed to start.
5.12 OVERCURRENT
The operation during an overcurrent condition is described in the ‘Overcurrent Detection and Hiccup
Mode’ section. In summary, when the controller detects 7 clock cycles of an overcurrent condition, the
upper and lower MOSFETs are turned off and the controller enters a 'hiccup' mode'. After seven soft start
cycles, normal switching is attempted. If the overcurrent has cleared, normal operation resumes, otherwise
the sequence repeats.
5.13 OUTPUT UNDERVOLTAGE PROTECTION
If the output voltage, as sensed by U23 of the Functional Block Diagram on the FB pin becomes less than
0.588 V, the undervoltage protection threshold (84% of V
REF
), the controller enters the hiccup mode as
described in the Overcurrent Detection and Hiccup Mode section.
5.14 OUTPUT OVERVOLTAGE PROTECTION
The TPS40140 includes an output overvoltage protection mechanism. This mechanism is designed to turn
on the low-side FET when the FB pin voltages exceeds the overvoltage protection threshold of 810-mV
(typical). The high-side FET turns off and the low-side FET turns on and stays on until the voltage on the
FB drops below the undervoltage threshold. The controller then enters a hiccup recovery cycle as in the
undervoltage case. The output overvoltage protection scheme is active at all times. If at any time when the
controller is enabled, the FB pin voltage exceeds the overvoltage threshold, the low-side FET turns on
until the FB pin voltage falls below the undervoltage threshold.
Output overvoltage is defined as any voltage greater than the regulation level that appears on the output.
Overvoltage protection is accomplished by the feedback loop monitoring the output voltage via the FB pin.
If, during operation the output voltage experiences an overvoltage condition the FB pin voltage rises and
the control loop turns the upper FET off and the lower FET is turned on until the output returns to set level.
This puts the overvoltage channel in a boost mode configuration and tends to cause the input voltage to
be boosted up.
If the output overvoltage condition exists prior to the controller PWM switching starting, i.e., no switching
has commenced, the overvoltaged channel does not start PWM switching. This controller allows for
operating with a pre-biased output. Since the output is greater than the regulation voltage, no PWM
switching occurs.
DESIGN HINT: Care must be taken to insure there is sufficient load on the input voltage to prevent
excessive boosting.
5.15 CLKFLT, CLKIO PIN FAULT
If the CLKIO signal is to be distributed from the master to the slave controllers, and is not there, the slave
controller enters a ‘Standby’ mode. The upper and lower MOSFETs are turned off but the internal 5-V
regulator is still active and VREG is present. The CLKIO signal could be turned off at the master controller
or the connection to the slave CLKIO input could be opened. If the CLKIO signal is restored, normal
operation continues.
5.16 PHSEL PIN FAULT
The PHSEL pin is normally terminated with a resistor string, or tied directly to ground. If this string
becomes open, the PHSEL pin voltage is pulled up internally to greater than 4V. The controller enters a
‘Standby’ mode. The upper and lower MOSFETs are turned off but the internal 5V regulator is still active
and VREG is present. If the PHSEL connection is restored, normal operation continues after 64 PWM
clock cycles.
20 APPLICATION INFORMATION Copyright © 2005–2013, Texas Instruments Incorporated
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