Datasheet

R
BIAS
+ 0.7
ǒ
R1
ǒ
V
OUT
* 0.7
Ǔ
Ǔ
COMP
+
R
BIAS
0.7 V
V
FB
V
OUT
UDG-05100
+
VOUT
GSNS
DIFFO
30 kW
30 kW
30 kW
30 kW
−
TPS40140
www.ti.com SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013
5.7 DIFFERENTIAL AMPLIFIER, U9
The unity gain differential amplifier has high bandwidth to achieve improved regulation at user defined
point of load and ease layout constrains. The output voltage is sensed between the VOUT and GSNS
pins. The output voltage programming divider is connected to the output of the amplifier, the DIFFO pin.
Figure 5-4. Differential Amplifier Configuration
DESIGN HINT: Because of the resistor configuration of the differential amplifier, the input impedance must
be kept very low or errors result in setting the output voltage.
5.8 POWER GOOD
The PGOOD1, PGOOD2 pins indicate when the inputs and output are within their specified ranges of
operation. Also monitored are the UVLO_CE1, UVLO_CE2 and TRK1 and TRK2 pins. The PGOOD has a
high impedance when indicating inputs and outputs are within specified limits and is pulled low to indicate
an out of limits condition. The PGOOD signal is held low until the respective TRK1 or TRK2 pin voltages
exceed 1.4 V, then the undervoltage, overcurrent or overtemperature controls the state of PGOOD.
5.9 SETTING THE OUTPUT VOLTAGE
Two resistors, R1 and R
BIAS
sets the output voltage as shown in Figure 5-5.
Figure 5-5. Setting the Output Voltage with R
BIAS
R
BIAS
is calculated in Equation 5.
(5)
5.10 PROGRAMMABLE INPUT UNDERVOLTAGE LOCK OUT PROTECTION
A voltage divider that sets 2 V on the UVLO_CEx pins determines when the controller begins to operate.
The internal regulators are enabled when the voltage on the UVLO_CEx pins exceeds 1 V, but switching
commences when the voltage is 2 V.
Copyright © 2005–2013, Texas Instruments Incorporated APPLICATION INFORMATION 19
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