Datasheet

R2 +
I
PK
DCR
eqv
Ac ) V
OS
)
0.9
V
IN
ǒ
0.5
V
IN
Ǔ 20 10
*6
+ 510 kW
R1 +
I
PK
DCR
eqv
Ac ) V
OS
)
0.9
V
IN
ǒ1 *
0.5
V
IN
Ǔ 20 10
*6
+ 22.5 kW
(eqv)
R2 DCR
DCR = × DCR =
R1+ R2 2
IN
(eqv) ramp sw
V × Ac
L
>
DCR 2 × V × f
TPS40140
SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013 www.ti.com
(41)
(42)
In this design, a 1-μF capacitor is placed at the CSRT1 pin for the purpose of eliminating noise. It can be
removed without degrading performance.
6.1.5.4 Overcurrent Protection (ILIM1 pin 34)
The resistor selection equations in the CALCULATING OVERCURRENT PROTECTION LEVELsection
are simplified to calculate the over current setting resistors. Set the DC over current rating at 25A.
(43)
(44)
where
• V
OS
is defined as the internal offset, typically V
RAMP
/ (2 × Nph)
• V
RAMP
is the ramp amplitude (0.5 V typ)
• Nph is 6 if V
PHSEL
= 1.6 V ±0.2 V, otherwise Nph = 8
6.1.5.5 VREG (pin 21)
A 4.7-μF capacitor is connected to VREG pin to filter noise.
6.1.5.6 BP5 (pin 8)
A 4.7Ω and 1μF capacitor is placed between VREG and BP5.
6.1.5.7 PHSEL (pin 4)
For this dual output configuration, the PHSEL pin is directly tied to GND. The channel 1 and channel 2 has
a 180° phase shift.
6.1.5.8 VSHARE (pin 6)
A 1μF capacitor is tied from VSHARE pin to GND.
6.1.5.9 PGOOD1 (pin 30)
The PGOOD1 pin is tied to BP5 with a 10-kΩ resistor.
6.1.5.10 UVLO_CE1 (pin 29)
It is connected to the input voltage with a resistor divider. The two resistors have the same value of 10-kΩ.
When the input voltage is higher than 2 V, the chip is enabled.
6.1.5.11 CLKIO (pin 28)
CLKIO is floating as no clock synchronization required for dual output configuration.
46 DESIGN EXAMPLES Copyright © 2005–2013, Texas Instruments Incorporated
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