Datasheet

M_CH1
M_CH1
M_CH2
M
M_CH1M_CH2
S_CH1
S_CH2
M_CH1M_CH2
S1_CH1 S2_CH1
S1_CH2S2_CH2
M_CH1M_CH2
S2_CH1
S1_CH2S2_CH2
S3_CH1
S4_CH1
S5_CH1
S3_CH2
S4_CH2
S5_CH2
M
R
S1
R
S2
S5
S3
S4
R
S1
R
S2
M
R
S3
S5
S6
S4
S7
R
S1
R
S2
M
R
S3
M
R
S1
R
S2
M
R
S
M_CH2
S1_CH1
S2_CH1
S1_CH2
S2_CH2
S3_CH1
S4_CH1
S5_CH1
S3_CH2
S4_CH2
S5_CH2
S6_CH1
S6_CH2
S7_CH2
S7_CH1
ILIM2=
h
i
Phase
PHSEL connection
Phase
M_CH1M_CH2
S1_CH1
S2_CH1
S1_CH2
S3_CH1
S3_CH2
S2_CH2
(A) TwoPhaseMaster
1 2 3 4 5 6 7 8
1 2 3 4 5 6
Clockscheme
(E) ‘Missing’ PulsewithsixandeightCLKIOpulses
PHSEL connection
(C)SixPhase,MasterandtwoSlaves
S1_CH1
(B) FourPhase, MasterandoneSlave
(D)EightPhase,MasterandthreeSlaves
(F) TwelvePhase , MasterandfiveSlaves
(G)SixteenPhase,MasterandsevenSlaves
TPS40140
www.ti.com SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013
5.28 DIGITAL CLOCK SYNCHRONIZATION
Figure 5-20 is a summary of the master and slave clock phasing. The master and the slaves can be
selected to be a multi-phase, single output configuration and/or several independent output voltage rails,
independent of the clocking.
Figure 5-20. Clock Phasing Summary
Copyright © 2005–2013, Texas Instruments Incorporated APPLICATION INFORMATION 39
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