Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers VQFN 36

HDRV1

SW1

LDRV1

HDRV2

TPS40140

SW2

LDRV2

CS1

VIN

CSRT1

CS2

VIN

CSRT2

VOUT1

VOUT2

UDG−06016

TPS40140

www.ti.com

SLUS660H –SEPTEMBER 2005–REVISED JUNE 2013

DUAL OR 2-PHASE, STACKABLE CONTROLLER

Check for Samples: TPS40140

1 INTRODUCTION

1.1 FEATURES

• VDD From 4.5 V to 15 V, With Internal 5-V

Regulator

1.2 APPLICATIONS

• V

OUT

From 0.7 V to 5.8 V

• Graphic Cards

• Converts From 15-V Input to 0.7-V Output at

• Internet Servers

1MHz

• Networking Equipment

• Dual-Output or 2-Phase Interleaved Operation,

Stackable to 16 Phases

• Telecommunications Equipment

• Supports Pre-Biased Outputs

• DC Power Distributed Systems

Programmable Switching Frequency Up to 1

MHz/Phase

• 0.5% Internally Trimmed 0.7-V Reference

• 10-μA Shutdown Current

• Current Mode Control with Forced Current

Sharing

(1)

• 1-V to 40-V Power Stage Operation Range

• Power Sharing from Different Input Voltage

Rails, (e.g. Master From 5 V, Slave From 12 V)

• True Remote Sensing Differential Amplifier

• Programmable Input Undervoltage Lockout

• Resistive or Inductor DCR Current Sensing

• Provide a 6-Bit Digitally-Controlled Output

When Used With TPS40120

• 36-pin QFN Package

(1) Patents Pending

1.3 DESCRIPTION

The TPS40140 is a multi-functional synchronous buck controller that can be configured to provide either a

single-output two-phase power supply or a power supply that supports two independent outputs. Several

TPS40140 controllers can be stacked up to a 16-phase multi-phase single output power supply.

Alternatively, several controllers providing multiple independent outputs can be synchronized in an

interleaving pattern for improved input ripple current.

The TPS40140 is capable of converting from a 15-V input to a 0.7-V output at 1MHz.

Each phase operates at a switching frequency of up to 1 MHz. The two phases in one device operate

180° out-of-phase. In a multiple device stackable configuration, the phase shift of the slaves, relative to a

master, is programmable.

1.4 ORDERING INFORMATION

PACKAGE PINS TRANSPORT MEDIA MINIMUM QUANTITY ORDERABLE DEVICE

Small tape and reel 250 TPS40140RHHT

Plastic Quad Flatpack RHH (PQFP) 36

Large tape and reel 3000 TPS40140RHHR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (71 pages)

PAGE 1
TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 DUAL OR 2-PHASE, STACKABLE CONTROLLER Check for Samples: TPS40140 1 INTRODUCTION 1.1 FEATURES 12 • VDD From 4.5 V to 15 V, With Internal 5-V Regulator • VOUT From 0.7 V to 5.8 V • Converts From 15-V Input to 0.7-V Output at 1MHz • Dual-Output or 2-Phase Interleaved Operation, Stackable to 16 Phases • Supports Pre-Biased Outputs Programmable Switching Frequency Up to 1 MHz/Phase • 0.5% Internally Trimmed 0.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 1 ......................................... 1 .......................................... 1 1.2 APPLICATIONS ..................................... 1 1.3 DESCRIPTION ...................................... 1 1.4 ORDERING INFORMATION ........................ 1 DEVICE RATINGS ....................................... 3 2.1 ABSOLUTE MAXIMUM RATINGS .................. 3 2.2 RECOMMENDED OPERATING CONDITIONS ..... 3 2.3 THERMAL INFORMATION ......................
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 2 DEVICE RATINGS 2.1 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VDD, UVLO ≤ VDD, RT, SS SW1, SW2 Input voltage range MIN MAX –0.3 16 –1 44 SW1, SW2, transient < 50 ns –5 BOOT1, BOOT2, HDRV1, HDRV2 –0.3 6.0 RT Electrostatic dischage V VSW + 6.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 4 www.ti.
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TPS40140 www.ti.com 2.4 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS –40°C ≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5, f SW = 300 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.5 12 15 V 1 10 μA 5.0 5.5 V VDD INPUT SUPPLY Operating Voltage Range Shutdown Current UVLO_CE1 = UVLO_CE2 =GND BP5 INPUT SUPPLY Operating Voltage Range 4.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5, f SW = 300 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5 6.0 7.3 μA 10 12.5 15 μA VOLTAGE TRACKING (TRK1, TRK2) After EN, before PWM and during hiccup mode SS source current After first PWM pulse Fault Enable Threshold (1) Internal Clamp Voltage 1.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 85°C, (unless otherwise noted), VVDD = 7 V, VBP5 = 5 V, UVLO_CE1, UCLO_CE2: 10 kΩ, Pullup to BP5, f SW = 300 kHz, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER GOOD PGOOD transition low threshold VFB rising relative to VREF 10% 12.5% 15% PGOOD transition low threshold VFB falling relative to VREF -15% -12.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 3 TYPICAL CHARACTERISTICS BP5 TURNOFF HYSTERESIS VOLTAGE vs TEMPERATURE BP5 TURNON THRESHOLD VOLTAGE vs TEMPERATURE 4.2660 VBP5 − BP5 Turnon Threshold Voltage − V VBP5 − BP5 Turnoff Hysteresis Voltage − mV 230.4 230.2 230.0 229.8 229.6 229.4 229.2 4.2655 4.2650 4.2645 4.2640 4.2635 4.2630 4.2625 4.2620 4.2615 229.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 4.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 DIFFERENTIAL AMPLIFIER VOLTAGE GAIN vs TEMPERATURE BP5 CURRENT vs TEMPERATURE 1.0055 3.1 1.0050 3.0 1.0045 IBP5 − BP5 Current − mA Voltage Gain 1.0040 1.0035 1.0030 VIN = 0.7 V 1.0025 1.0020 1.0015 VIN = 4.0 V 1.0010 2.9 2.8 2.7 2.6 2.5 1.0005 1.0000 −40 −25 −10 5 20 35 50 65 80 2.4 −40 −25 −10 95 110 125 5 20 35 50 65 80 Figure 3-6.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com DIFFERENTIAL AMPLIFIER INPUT OFFSET VOLTAGE vs TEMPERATURE 4.0 HDRV SOURCE AND SINK RESISTANCE vs TEMPERATURE 3.5 3.0 RHDRV − Drive Resistance − Ω DIFFAMP Input Offset Voltage − mV 3.5 3.0 2.5 2.0 1.5 1.0 Source 2.5 2.0 Sink 1.5 0.5 0 −40 −25 −10 5 20 35 50 65 80 1.0 −40 −25 −10 5 95 110 125 TJ − Junction Temperature − °C 20 35 50 65 80 95 110 125 TJ − Junction Temperature − °C Figure 3-10. Figure 3-9.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 VSHARE VOLTAGE vs TEMPERATURE 5.30 2.0 5.28 1.8 5.26 VVSHARE − VSHARE Voltage − V VVREG − Output Regulation Voltage − V VREG OUTPUT VOLTAGE vs TEMPERATURE ILOAD = 66 mA 5.24 5.22 5.20 5.18 5.16 No Load 5.14 1.6 ILOAD = 189 µA 1.4 1.2 No Load 1.0 0.8 0.6 0.4 0.2 5.12 5.10 −40 −25 −10 5 20 35 50 65 80 95 110 125 0.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 4 DEVICE INFORMATION 4.1 TERMINAL CONFIGURATION The package is an 36-pin PQFP (RHH) package. The thermal pad is an electrical ground connection.
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TPS40140 www.ti.com 4.3 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 VOLTAGE MASTER AND VOLTAGE SLAVE A voltage master has the channel that monitors the output voltage and generates the 'COMP' signal for voltage regulation. A Voltage slave channel is configured by connecting the TRKx pin to BP5. Then the COMP signal from the master is connected to the COMPx pin on the Voltage slave.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com Table 4-1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION PGOOD2 15 O Power good indicators for CH2 output voltage. This open-drain output connects to a voltage via an external resistor PGND 23 - Power ground reference for the controller lower gate drivers. There should be a high current return path from the sources of the lower MOSFETs to this pin. PHSEL 4 O A 20μA current flows from this pin.
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TPS40140 www.ti.com 4.4 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 FUNCTIONAL BLOCK DIAGRAM BP5 TPS40140 U1 V5REG VDD 17 21 VREG U4 RAMP1 8 CS1 31 + + U5 27 BOOT1 PWM1 U8 U3 ICTLR1 CSRT1 32 2 GSNS 3 DIFFO 1 FB1 36 + U12 + + + U11 U10 OC1 6 mA to 12 mA OC2 FB1 + + U14 + U15 – 6 mA to 12 mA U20 U23 UV/OV/OC Control 18 BOOT2 FB2 0.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 5 APPLICATION INFORMATION 5.1 FUNCTIONAL DESCRIPTION The TPS40140 operates with a programmable fixed switching frequency. It is a current feedback controller with forced phase current balancing. When compared to voltage mode control, the current feedback controller results in a simplified feedback network and reduced input line sensitivity.
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TPS40140 www.ti.com 5.4 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 TRACK (SOFT-START WITHOUT PRE-BIASED OUTPUT) A capacitor connected to the TRKx pins sets the power-up time. When UVLO_CEx is high and the internal power-on reset (POR) is cleared, the calibrated current source, starts charging the external soft start capacitor with 12-μA. The PGOOD pin is held low during the start up. The rising voltage across the capacitor serves as a reference for the error amplifier, U10 and U14.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 2.4 1.4 12 µA FBx 0.7 FBx TRKx 6 µA 0 VOUT VPRE-BIAS VOUT PGOOD 0 t0 t1 t2 t3 UDG-12121 Figure 5-2. Soft-Start with Pre-Biased Output Waveforms From CSx Amplifier VOUT VREF 0.7 V R1 FBx TRKx RBIAS Error Amplifier Ramp1 + COMPx + U3 + + 12 µA CEXT PWM Logic + 6 µA U7 Comparator + UDG−06031 Figure 5-3.
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TPS40140 www.ti.com 5.7 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 DIFFERENTIAL AMPLIFIER, U9 The unity gain differential amplifier has high bandwidth to achieve improved regulation at user defined point of load and ease layout constrains. The output voltage is sensed between the VOUT and GSNS pins. The output voltage programming divider is connected to the output of the amplifier, the DIFFO pin. 30 kW VOUT + DIFFO − 30 kW 30 kW GSNS 30 kW Figure 5-4.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 5.11 POWER ON RESET (POR) The internal POR function ensures the VREG and BP5 voltages are within their regulation windows before the controller is allowed to start. 5.12 OVERCURRENT The operation during an overcurrent condition is described in the ‘Overcurrent Detection and Hiccup Mode’ section.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 5.17 OVERTEMPERATURE If the temperature of the controller die is detected to be above 155°C, the upper and lower MOSFETs are turned off and the 5-V regulator, VREG, is turned off. When the die temperature decreases 30°C the controller performs a normal start up. 5.18 FAULT MASKING OPERATION If the TRKx pin voltage is externally limited below the 1.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com PHASE FREQUENCY vs TIMING RESISTOR 450 400 RT- Timing Resistor (k 350 300 250 200 150 100 50 0 100 200 300 400 500 600 700 800 900 1000 Phase Switching Frequency (kHz) C001 Figure 5-6. Phase Switching Frequency vs Timing Resistance 5.21 SYNCHRONIZING A SINGLE CONTROLLER TO AN EXTERNAL CLOCK The TPS40140 has the ability to synchronize a single controller to an external clock.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 in the 6th or 8th position. With the missing pulse, the phase synchronization of the master, to the missing pulse, can be controlled by the voltage on the PHSEL pin. See the section on DIGITAL CLOCK SYNCHRONIZATION. Phase shifting would also be desirable if more than one controller were to be synchronized to the same external clock. The high-level threshold for the external clock is 3.2 V, and the low-level threshold is 0.5 V.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com R SNS VOUT IOUT CSn + CSRTn VC – + + COMP U1 CS gain = 12. 5 + U2 Error Amplifier – U3 Ve + VSHARE Ramp 1.8 V 0.5 V U4 PWM + U5 + 0V R1 U6 20 µA ILIM + U7 Overcurrent R2 UDG-12122 VOUT Figure 5-8. Output Current Sensing and Overcurrent Detection The output current, IOUT, flows through RSNS and develops a voltage, VC across it, representative of the output current.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 High bandwidth current amplifiers, U2 and U21 can accept as an input voltage either the voltage drop across dedicated precise current sense resistors, or inductor’s DCR voltage derived by an RC network, or thermally compensated voltage derived from the inductor’s DCR.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com In Figure 5-9, normal operation is occurring between t0 and t1 as shown by VOUT being at the regulated voltage, ©) and normal switching on the SW NODE (B) and COMP at it's nominal level, (D). At t1, an overcurrent load is experienced. The increased current forces COMP to increase to the ILIM level as shown in (D). If the COMP voltage is above the ILIM voltage for 7 switching cycles, the controller enters a hiccup mode.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 VOUT TPS40140 R2 ILIMx R1 VSHARE UDG-12123 Figure 5-10. Selecting Overcurrent Threshold Resistors, R2 and R1 The two factors, alpha and beta help simplify the final equations and are given by Equation 13 and Equation 14. V a + RAMP V IN (13) b + DCR AC I PEAK ) ǒ Ǔ V RAMP 2 Nph (14) R1 is shown in Equation 15. b ) a V SH R1 + (1 * a) I LIM (15) R2 is shown in Equation 16.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 5.27 CONFIGURING SINGLE AND MULTIPLE ICS The controller may be configured for a single output, 2-phase mode or a dual output voltage mode. In the dual output mode the input voltages and the output voltages are independent of each other. In 2-phase mode the input voltages and output voltages are tied together, respectively and certain other pins must be configured. The two phases of a single controller are always 180° out-of-phase.
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TPS40140 www.ti.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 5.27.2 MULTIPLE ICs In a multiple device system it is often desirable to synchronize the clocks each device to minimize input ripple current as well as radiated and conducted emissions. This is accomplished by designating one of the controllers as the 'master' and the other devices as 'slaves'. The master generates the system clock, CLKIO , and it is distributed to the slaves.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com Figure 5-13. Typical Applications Circuit, 4-Phase Mode In this configuration, the master senses that there is one slave controller, by the 39-kΩ resistor on the PHSRL pin, and distributes the CLKIO signal. The slave controller senses the zero-volt level on its PHSEL pin and delays the proper number of CLKIO pulses to be 90° out-of-phase with the master.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 Two ICs could also be configured as a 2-phase, single output master and a slave which has two independent outputs, but is synchronized with the master controller clock. The configuration is shown in Table 5-5. Table 5-5.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 5.27.3.2 Two ICs Operation To increase the total current capability, or number of outputs, a single slave controller can be added as shown in Figure 5-15 TPS40140 MASTER 20 mA PHSEL CLKIO TPS40140 R1 CLKIO PHSEL SLAVE1 10 kW Figure 5-15. Master Controller and One Slave Controller, Four Phases In this configuration, the master senses that there is one slave controller, and distributes the CLKIO signal.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 5.27.3.3 Three ICs Operation To increase the total current capability to six phases, or to increase the number of outputs, two slave controllers can be added as shown in Figure 5-16. In this configuration for perfect interleaving, the master and slaves are 120° out-of-phase. The CLKIO signal has six clocks for each cycle of the switching period; therefore, the switching period is reduced.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com TPS40140 MASTER 20 mA PHSEL CLKIO TPS40140 R3 CLKIO PHSEL SLAVE3 TPS40140 R2 CLKIO PHSEL SLAVE2 TPS40140 R1 CLKIO PHSEL SLAVE1 10 kW Figure 5-17. Master Controller and Three Slave Controllers, Eight Phases In this configuration, the master senses that there are three slave controllers, and distributes a eightphase CLKIO signal.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 5.27.3.5 Six ICs Operation To further increase the total current capability to twelve phases, or to increase the number of outputs, five slave controllers can be added as shown in Figure 5-18 TPS40140 MASTER 20 mA BP5 TPS40140 PHSEL CLKIO CLKIO ILIM2 PHSEL SLAVE5 TPS40140 ILIM2 TPS40140 R2 CLKIO CLKIO PHSEL PHSEL SLAVE4 SLAVE2 TPS40140 ILIM2 TPS40140 R1 CLKIO CLKIO PHSEL SLAVE3 PHSEL SLAVE1 10 kW Figure 5-18.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 5.27.3.6 Eight ICs Operation To further increase the total current capability to sixteen phases, or to increase the number of outputs, seven slave controllers can be added as shown in Figure 5-19.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 5.28 DIGITAL CLOCK SYNCHRONIZATION Figure 5-20 is a summary of the master and slave clock phasing. The master and the slaves can be selected to be a multi-phase, single output configuration and/or several independent output voltage rails, independent of the clocking.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 5.28.1 BASIC CONFIGURATIONS FOR 2, 4, 6, 8, 12 OR 16 PHASES The solid square boxes in Figure 5-20 represent the PHSEL pin of the master (M) controller or a numbered slave controller (S1-S7). The labels on the spokes of the wheels indicate a master Channel 1 and master Channel 2 (M_CH1 and M_CH2) and numbered slaves Channel 1 and slave Channel 2 (Sn_CH1 and Sn_CH2).
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 PHSEL connection Phase ILIM 2 = hi M S1_CH1 S4 S4_CH1 M_CH2 R S1 S2_CH1 S5_CH1 NOT USED R S2 S3_CH1 M_CH1 S5_CH2 NOT USED S4_CH2 S3 S2_CH2 S3_CH2 S1_CH2 Figure 5-22. Ten-Phase System with Slaves Not Attached Clocking between the attached slave channels is as shown. 5.29 DESIGN EXAMPLES INFORMATION 5.29.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com VIN L1 DCR VOUT C1 R1 R2 + VC − To CSRTx To CSx Figure 5-24. Using Resistor R2 to Reduce the Current Sense Amplifier Voltage 42 The parallel combination of R1 and R2 is shown in Equation 19. L1 R1 ø R2 + DCR C1 (19) The ratio shown in Equation 20 provides the required voltage attenuation.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 6 DESIGN EXAMPLES 6.1 Example 1: Dual-Output Configuration from 12 V to 3.3 V and 1.5 V DC-to-DC Converter Using a TPS40140 The following example illustrates the design process and component selection for a dual output synchronous buck converter using TPS40140. The design goal parameters are given in Table 6-1. Only the calculated numbers for the 1.5-V output are shown, however, the equations are suitable for both channel design.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 ESRCo = www.ti.com VRIPPLE(TotOUT) - VRIPPLE(COUT) IRIPPLE æ ö IRIPPLE VRIPPLE(TotOUT) - ç ÷ 8×COUT × fSW ø è = IRIPPLE (24) With 880-μF output capacitance, the ripple voltage at the capacitor is calculated to be 863-μV. In the specification, the output ripple voltage should be less than 30 mV, so based on Equation 24, the required maximum ESR is 9.5 mΩ. The selected capacitors can meet this requirement. 6.1.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 The calculated total loss in the high-side MOSFET is: P SWtot + PSWcond ) PSWsw + 0.91 W (31) The power losses in the low-side SR MOSFET is calculated Equation 32: missin g equation (32) The RMS current in the low-side MOSFET is shown in Equation 33. I SRrms + Ǹ (1 * D) ǒ I OUT 2 I ) RIPPLE 12 Ǔ 2 + 18.7 A (33) The RDS(on) is 4 mΩ when the MOSFET gate voltage is 4.5 V.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com VIN × Ac L > DCR(eqv) 2 × Vramp × fsw (41) DCR (eqv) = R2 DCR × DCR = R1+ R2 2 (42) In this design, a 1-μF capacitor is placed at the CSRT1 pin for the purpose of eliminating noise. It can be removed without degrading performance. 6.1.5.4 Overcurrent Protection (ILIM1 pin 34) The resistor selection equations in the CALCULATING OVERCURRENT PROTECTION LEVELsection are simplified to calculate the over current setting resistors.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 6.1.5.12 BOOT1 and SW1 (pin 27 and 25) A bootstrap capacitor is connected between the BOOT1 and SW1 pin. The bootstrap capacitor depends on the total gate charge of the high side MOSFET and the amount of droop allowed on the bootstrap capacitor. Cboot = Qg 8nc = = 16nF ΔV 0.5V (45) For this application, a 0.1-μF capacitor is selected. 6.1.5.13 TRK1 (pin 33) A 22-nF capacitor is tied to TRK1 pin to provide 1.28-ms of soft-start time.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com VREF R2 C1 R1 + C2 Figure 6-1. Type II Compensator The compensator transfer function is: Gc(s) = 1 s × (R1+ R2) × C1+ 1 × R1× C2 s × (s × R2 × C1+ 1) (51) The loop gain transfer function is: Tv(s) = Gc(s) × Gvc(s) (52) Assume the desired crossover frequency is 60 kHz, then set the compensator zero about 1/10 of the crossover frequency and the compensator pole equal to the ESR zero.
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TPS40140 www.ti.com 6.1.7 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 Design Example Summary + + + + + + + + Figure 6-2 shows the schematic of the dual output converter design. Figure 6-2.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 6.2 www.ti.com Example 2: Two-Phase Single Output Configuration From 12 V to 1.5 V DC/DC Converter Using a TPS40140 The following example illustrates the design process and component selection for a two-phase single output synchronous buck converter using TPS40140. The design goal parameters are given in Table 6-2. The inductor and MOSFET selection equations are quite similar to the dual output converter design, so they are not repeated here.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 Another important consideration for the input capacitor is the RMS ripple current rating. Due to the interleaving of multi-phase, the input RMS current is reduced. The input ripple current RMS value over load current is calculated in Equation 59.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 6.2.3.7 www.ti.com PGOOD1 and PGOOD2 (pin 30 and pin 15) Both of PGOOD1 and PGOOD2 are tied to BP5 with a 10-kΩ resistor. 6.2.3.8 CLKIO (pin 28) CLKIO is open as no clock synchronization required for two phase configuration. 6.2.3.9 DIFFO, VOUT and GSNS (pin 1, pin 2 and pin 3) VOUT and GSNS should be connected to the remote sensing output connector. DIFFO is connected to the feedback resistor divider.
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TPS40140 www.ti.com 6.2.4 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 Design Example Summary + + + + Figure 6-3 shows the schematic of the two phase single output converter design. Figure 6-3.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 6.3 www.ti.com Example 3: Four-Phase Single Output Configuration From 12 V to 1.8 V DC-to-DC Converter Using Two TPS40140 The following example illustrates the design process and component selection for a four phase single output synchronous buck converter using two TPS40140. Here, two modules are designed. One is a master module. The other one is a slave module. Each module contains two phases and each phase handle 5-A.
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TPS40140 www.ti.com 6.3.3 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 Step 3: Peripheral Component Design 6.3.3.1 Master Module 6.3.3.1.1 RT (pin 5) It is connected to GND with a resistor that sets the switching frequency. R + 1.33 ǒ39.2 10 3 Ǔ f *1.041 * 7 + 52.2 kW SW (62) Here, fswrepresents the phase switching frequency. In the design, a 47-kΩ resistor is selected. The actual switching frequency is 650 kHz. 6.3.3.1.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 6.3.3.2.5 FB1 and FB2 (pin 36 and pin 9) Both FB1 and FB2 are connected to GND. 6.3.3.2.6 PHSEL (pin 4) The PHSEL pin is directly tied to GND. 6.3.3.2.7 PGOOD1 & PGOOD2 (pin 30 & pin 15) Both of PGOOD1 and PGOOD2 are tied to BP5 with a 10-kΩ resistor. 6.3.3.2.8 CLKIO (pin 28) CLKIO is connected to the master module CLKIO. 6.3.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 Figure 6-4.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com Figure 6-5.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 S1 VIN J1 VOUTTP1 1 VOUT PHSELIN VOUT VINTP1 NC 2 3 4 R3 39 kW C2 180 mF C1 47 mF GND GND GNDTP5 GNDTP3 CLKIO VIN CLKIO VIN 10 kW PHSELIN COMP1 VSHR Master GND COMP1 VSHR GND Slave VOUT GND VOUT UDG-08085 Figure 6-6.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 6.4 www.ti.com ABBREVIATIONS Table 6-4.
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TPS40140 www.ti.com 6.5 6.5.1 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 LAYOUT CONSIDERATIONS Power Stage A synchronous BUCK power stage has two primary current loops – The input current loop which carries high AC discontinuous current while the output current loop carries high DC continuous current. The input current loop includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground path back to the input capacitors.
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TPS40140 SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 www.ti.com 7 ADDITIONAL REFERENCES 7.1 Related Devices The following devices have characteristics similar to the TPS40140 and may be of interest. DEVICE 7.2 DESCRIPTION TPS40130 Two-Phase Synchronous Buck Controller with Integrated MOSFET Drivers TPS40090 4-Channel Multi-Phase DC/DC Controller with Three State TPS40120 Feedback Divider, Digitally Controlled References These references may be found on the web at www.power.ti.
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TPS40140 www.ti.com SLUS660H – SEPTEMBER 2005 – REVISED JUNE 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (September 2009) to Revision G • • • • • Added Added Added Added Added Page clarity to Section 4.4 ........................................................................................................ 2 updated Thermal Information table .................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS40140RHHT Package Package Pins Type Drawing VQFN RHH 36 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 16.4 Pack Materials-Page 1 6.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.3 1.1 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40140RHHT VQFN RHH 36 250 210.0 185.0 35.
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