Datasheet

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UDG−04030

Power-On Reset

U13

5 µA

PWM

LOGIC

BP5

AGND

CS1

CSRT1

PWM1

TPS40130DBT

VOUT

GSNS

DIFFO

VREF

DROOP

COMP

CS2

CSRT2

ILIM

UVLO

EN/SYNC

OVSET

ICTLR

U12

U18

U11

0.7 V

Ramp1

PWM2

U19

OC/UV

Detect

U15

PGOOD

VIN5

BP5

U23

Clock

U22

Power−On Reset

U25

OV Detect

U24

Ramp Gen

Ramp1

Ramp2

U20

SSUV

29 LDRV2U21

U17 27 HDRV2

26 BOOT2

28 SW2

VIN5

1 LDRV1

2 VIN5

30 PGND

U10

Anti

Cross

Conduction

4 HDRV1

5 BOOT1

3 SW1

U16

Anti

Cross

Conduction

Ramp2

U14

20 kΩ

FUNCTIONAL DESCRIPTION

TPS40130

SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005

FUNCTIONAL BLOCK DIAGRAM

The TPS40130 uses programmable fixed-frequency, peak current mode control with forced phase current

balancing. When compared to voltage-mode control, current mode results in a simplified feedback network and

reduced input line sensitivity. Phase current is sensed by using either the DCR (direct current resistance) of the

filter inductors or current sense resistors installed in series with output. The first method involves generation of a

current signal with an R-C circuit (shown in the applications diagram). The R-C values are selected by matching

time constants of the RC circuit and the inductor time constant, R×C = L/DCR. With either current sense

method, the current signal is amplified and superimposed on the amplified voltage error signal to provide current

mode PWM control.

Output voltage droop can be programmed to improve the transient window and reduce size of the output filter.

Other features include: a true differential output sense amplifier, programmable current limit, programmable

output over-voltage set-point, capacitor set soft-start, power good indicator, programmable input undervoltage

lockout (UVLO), user programmable operation frequency for design flexibility, external synchronization

capability, programmable pulse-by-pulse overcurrent protection, output undervoltage shutdown and restart.

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