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t − Time − 4 ms/div

(1 V/ div)

(200 mV / div)

L2,

(10 A / div)

(1 V/div)

(200 mV/ div)

= 0.588 V

t − Time − 40 µs/div

L2,

(10 A / div)

LAYOUT CONSIDERATIONS

Introduction

Two Ground Planes

Low-Level Signal Connections and Routing

Current Sense Signals

TPS40130

SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005

TYPICAL CHARACTERISTRICS (continued)

Figure 27. Overcurrent, Hiccup Mode Figure 28. Overcurrent

Any pin number references are for the DBT, TSSOP package. There are two general classes of signals to

consider for proper layout, high-current switching and low-level analog. Refer to Figure 13 for references to

components. A printed wiring board (PWB) with a minimum of four layers should be used.

A basic requirement is two separate ground planes that ultimately get connected together at a point where no

switching currents are present, the power ground (PGND) and the analog ground (AGND). They should be

implemented as split planes on the top and bottom layers. The PGND is used for all high-current signals

including LDRV1, LDRV2, lower MOSFETs and input and output decoupling capacitors. PGND should be used

on the top layer around the high current components and on the bottom layer as a minimum. The AGND is used

for low level signals such as: soft-start, R

, VREF, FB, BP5 decoupling to AGND. AGND should be used on the

top layer around the device and low level components and on the bottom layer as a minimum. The signals which

connect to the two different ground planes are shown in Figure 13 using different symbols for each ground.

Using inductor current sense has advantages over using a low-value, high-power current-sense resistor, but

attention must be paid to how the current sense signals are generated and routed.

Connection

Resistor R2 and capacitor C5 generate the current sense signal for phase 1 and resister R1 and capacitor C4

generate the current sense signal for phase 2. The R2-C5 and R1-C4 components must be connected directly to

the pads for L1 and L2, respectively.

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